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NTHU-CS VLSI/CAD LAB TH EDA De-Shiuan Chiou Da-Cheng Juan Yu-Ting Chen Shih-Chieh Chang Department of CS, National Tsing Hua University, Taiwan Fine-Grained.

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Presentation on theme: "NTHU-CS VLSI/CAD LAB TH EDA De-Shiuan Chiou Da-Cheng Juan Yu-Ting Chen Shih-Chieh Chang Department of CS, National Tsing Hua University, Taiwan Fine-Grained."— Presentation transcript:

1 NTHU-CS VLSI/CAD LAB TH EDA De-Shiuan Chiou Da-Cheng Juan Yu-Ting Chen Shih-Chieh Chang Department of CS, National Tsing Hua University, Taiwan Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

2 2 Outline Sleep Transistor Sizing Problem Sleep Transistor Sizing Problem MIC Estimation Mechanism MIC Estimation Mechanism Partitioned Time-Frame for MIC Estimation Partitioned Time-Frame for MIC Estimation Experimental Results and Conclusions Experimental Results and Conclusions

3 3 Power Gating Leakage increases exponentially Leakage increases exponentially –reach 50% of total power in 65nm technology Power Gating Power Gating – reduce leakage –One of the most effective ways to reduce leakage Low V th Logic Device VDD GND use high V th Sleep Transistor to reduce the leakage current SL VGND GND

4 4 C1C1 C2C2 C3C3 Implementation of Power Gating Distributed Sleep Transistor Network (DSTN) Distributed Sleep Transistor Network (DSTN) VDD VGND Low V th Logic Device SL

5 5 Leakage Saving In standby mode: In standby mode: –Leakage: proportional to the ST ’ s size –Small ST to reduce leakage I leakage VDD VGND I leakage

6 6 Voltage Drop across the ST In active mode: In active mode: –Voltage drop across a ST degrades the speed –Voltage drop: inversely proportional to the ST ’ s size –Large ST to bound the voltage drop V ST VDD VGND V ST

7 7 V ST * Sleep Transistor (ST) Sizing Dilemma scenario: Dilemma scenario: –Large ST to bound the voltage drop. (active mode) –Small ST to reduce leakage. (standby mode) =>objective: minimize ST size (leakage) under a specified voltage drop constraint, V ST * V ST VDD VGND V ST V ST *

8 8 C1C1 C2C2 C3C3 Estimate Voltage Drop by MIC Maximum Instantaneous Current (MIC) through the ST Maximum Instantaneous Current (MIC) through the ST –determines the worst case voltage drop Estimating the upper bound of MIC(ST) Estimating the upper bound of MIC(ST) –for sizing ST appropriately to meet voltage drop constraint MIC(ST 1 ) VDD VGND MIC(ST 2 ) MIC(ST 3 ) MIC(ST): MIC across a ST.

9 9 C1C1 C2C2 C3C3 Estimate Voltage Drop by MIC MIC(C) (MIC of a cluster) is easy to measure MIC(C) (MIC of a cluster) is easy to measure Due to current balancing effect Due to current balancing effect –MIC(ST) (MIC through the ST) is hard to predict MIC(ST 1 ) VDD VGND MIC(ST 2 ) MIC(ST 3 ) MIC(C 1 ) Finding the MIC of a cluster is fast Finding the MIC across a ST is time-consuming

10 10 Temporal Perspective of Clusters ’ MIC Traditional ways Traditional ways –use the entire clock period ’ s MIC to determine the ST size (Time Unit) Cluster 1 Cluster 2 MIC(C 2 ) occurs at T 9 one clock cycle MIC(C i ) waveform (Current) MIC(C 1 ) occurs at T 6

11 11 (Time Unit) Current (mA) Cluster 1 Cluster 2 Temporal Perspective of Clusters ’ MIC one clock cycle MIC(C i ) waveform Smaller time frames leads to: Smaller time frames leads to: –a more accurate MIC estimation –high computation complexity

12 12 Difficulties Current balancing effect complicates the sizing problem Current balancing effect complicates the sizing problem Time-frame partitioning leads to high computation complexity Time-frame partitioning leads to high computation complexity MIC one clock cycle

13 13 Contributions A more accurate MIC prediction in a temporal perspective A more accurate MIC prediction in a temporal perspective A variable-length partitioning to reduce computation complexity A variable-length partitioning to reduce computation complexity Heuristics to minimize the size of sleep transistors Heuristics to minimize the size of sleep transistors Achieving 21% reduction in sleep transistor area Achieving 21% reduction in sleep transistor area

14 14 Outline Sleep Transistor Sizing Problem Sleep Transistor Sizing Problem MIC Estimation Mechanism MIC Estimation Mechanism Partitioned Time-Frame for MIC Estimation Partitioned Time-Frame for MIC Estimation Experimental Results and Conclusions Experimental Results and Conclusions

15 15 Resistance Network I(ST 1 ) I(ST 2 ) I(ST 3 ) I(C1)I(C1) I(C2)I(C2) I(C3)I(C3) R(ST 1 ) R(ST 2 ) R(ST 3 ) RVRV RVRV C1C1 C2C2 C3C3

16 16 The discharging ratio can be calculated by The discharging ratio can be calculated by –Kirchhoff ’ s Current Law –Ohm ’ s Law Discharging Ratio 9 8 10 2 2 C1C1 C2C2 C3C3 0.43 I(C 1 ) 0.34 I(C 2 ) 0.23 I(C 3 ) I(C1)I(C1)

17 17 Discharging Matrix Ψ → where I(ST 1 ) I(ST 2 ) I(ST 3 ) I(C1)I(C1) I(C2)I(C2) I(C3)I(C3) C1C1 C2C2 C3C3

18 18 MIC(ST) Estimation Mechanism → MIC(ST 1 ) MIC(ST 2 ) MIC(ST 3 ) MIC(C 1 ) MIC(C 2 ) MIC(C 3 ) C1C1 C2C2 C3C3 where

19 19 Outline Sleep Transistor Sizing Problem Sleep Transistor Sizing Problem MIC Estimation Mechanism MIC Estimation Mechanism Partitioned Time-Frame for MIC Estimation Partitioned Time-Frame for MIC Estimation Experimental Results and Conclusions Experimental Results and Conclusions

20 20 Temporal Perspective of Clusters ’ MIC Different MIC(C i ) occurs at different time points (Time Unit) Cluster 1 Cluster 2 MIC(C 2 ) occurs at T 9 one clock cycle MIC(C i ) waveform (Current) MIC(C 1 ) occurs at T 6

21 21 Temporal Perspective of Clusters ’ MIC Different MIC(C i ) occurs at different time points within a clock period Traditional way to estimate MIC(ST i ) is over pessimistic

22 22 Time-Frame Partitioning for MIC(ST) Estimation Expand MIC(C i ) into MIC(C i,T j ) (Time Frame) Cluster 1 Cluster 2 one clock cycle MIC(C i,T j ) waveform (Current) MIC(C 1,T 1 ) MIC(C 2,T 1 ) MIC(C 1,T 3 ) MIC(C 2,T 3 ) MIC(C 1,T 6 ) MIC(C 2,T 6 )

23 23 For each time frame T j, use MIC(C i,T j ) to obtain MIC(ST i,T j ) Time-Frame Partitioning for MIC(ST) Estimation

24 24 Time-Frame Partitioning for MIC(ST) Estimation For ST 1, the maximum MIC(ST 1,T j ) among all T j is the upper bound of MIC(ST 1 ) after partitioning Cluster 1 Cluster 2 (Time Frame) one clock cycle MIC(ST i,T j ) waveform MIC(ST 1 ) ST 1 ST 2 (Current) MIC(ST 2 )

25 25 Time-Frame Partitioning for MIC(ST) Estimation Cluster 1 Cluster 2 (Time Frame) one clock cycle MIC(ST i,T j ) waveform MIC(ST 1 ) ST 1 ST 2 MIC(ST 2 ) (Current) ORIGINAL_MIC(ST 1 ) 37% larger! ORIGINAL_MIC(ST 2 ) 27% larger! Time-Frame Partitioning leads to a better MIC(ST) estimation!

26 26 Reduce the Computation Complexity Increase the number of time frames leads to Increase the number of time frames leads to –more accurate voltage drop estimation –high computation complexity Reduce the computation complexity: Reduce the computation complexity: –dominated time-frame removal –variable length time-frame partitioning

27 27 Dominated Time-Frame Removal T 3 is dominated by T 6 T 3 is dominated by T 6 –MIC(C 1,T 6 ) > MIC(C 1,T 3 ) –MIC(C 2,T 6 ) > MIC(C 2,T 3 ) Neglect T 3 and all dominated time frames Neglect T 3 and all dominated time frames Cluster 1 Cluster 2 MIC(C 1,T 6 ) MIC(C 1,T 3 ) MIC(C 2,T 6 ) MIC(C 2,T 3 )

28 28 (T b dominates T c ) and (T b dominates T d ) (T b dominates T c ) and (T b dominates T d ) => the estimated upper bound will be smaller If all the MIC(C i ) are separated, the MIC(ST i ) can be better estimated! If all the MIC(C i ) are separated, the MIC(ST i ) can be better estimated! Variable Length Time-Frame Partitioning TaTa uniform two-way partition variable length two-way partition TbTb TdTd TcTc MIC(C 1,T b ) MIC(C 2,T b ) MIC(C 1,T d ) MIC(C 2,T d )MIC(C 1,T c ) MIC(C 2,T c ) (1) (2)

29 29 Problem Formulation of ST Sizing Inputs: Inputs: 1.Voltage-drop constraint 2.MIC(C i,T j ): Clusters ’ MIC information Objective: minimize the total ST width Objective: minimize the total ST width Voltage drops must meet the constraint Voltage drops must meet the constraint

30 30 ST Sizing Algorithm 99 1. Initialize ST size with a large value. MIC(ST i,T j ) = ． MIC(C i,T j ) V(ST i,T j ) = MIC(ST i,T j ) ． R(ST i ) 3. Update MIC(ST i,T j ) and voltage drops. Return ST size Yes Voltage drops ok? 0.38 0.30 0.21 0.18 0.27 0.30 0.21 0.18 0.21 0.24 0.35 0.28 0.14 0.16 0.23 0.36 = 2. Update the discharging matrix. No 4. Resize ST with the worst drop. 99 7399

31 31 Outline Sleep Transistor Sizing Problem Sleep Transistor Sizing Problem MIC Estimation Mechanism MIC Estimation Mechanism Partitioned Time-Frame for MIC Estimation Partitioned Time-Frame for MIC Estimation Experimental Results and Conclusions Experimental Results and Conclusions

32 32 Environment Setup TSMC 130nm CMOS technology TSMC 130nm CMOS technology Vdd = 1.3 volt Vdd = 1.3 volt Specified tolerable IR drop: 5% of the ideal supply voltage Specified tolerable IR drop: 5% of the ideal supply voltage MIC(C i,T j ) is obtained via 10,000-random-pattern PrimePower simulations MIC(C i,T j ) is obtained via 10,000-random-pattern PrimePower simulations

33 33 Implementation Flow RTL netlist SDF file Gate Positioning Gate location VCD Partitioning Partitioned VCD file : Our tools : Commercial tools Synthesis Gate-level netlist MIC Estimation V-length Partitioning (Optional) ST size ST Sizing Simulation VCD file Placement DEF file

34 34 Experimental Results Avg. AES des t481 i8 frg2 dalu C7552 C5315 C3540 C1355 C880 C499 C432 Circuit 18.091.0611.261.70 35242837928137272293396544378 1180832181457850976611804 1514162895402502473899405 1080772081417836993113247 1367012255223228353632 48338162283211029043468 28961721625621242692950041016 21901383019534187852377329794 9421685620282186502302029808 422251411496105911305619352 3452561967692331129615050 568364472296684834710741 495426270866775849112817 V-TPTPV-TPTP[2][8] Runtime (Sec.)Total Area (Width in μm) Previous works: [2] Chiou et al. DAC’06, [8] Long et al. DAC’03

35 35 Conclusions Propose an efficient sleep transistor sizing method for DSTN power gating designs Propose an efficient sleep transistor sizing method for DSTN power gating designs Present theorems based on temporal perspective for estimating a tight upper bound of voltage drop Present theorems based on temporal perspective for estimating a tight upper bound of voltage drop Achieving 21% size (leakage) reduction Achieving 21% size (leakage) reduction

36 36 Thank You!

37 37 Sleep Transistor (ST) Sizing Relations between W ST, and V ST. Relations between W ST, and V ST. Sleep Transistors operate in linear region in active mode. Sleep Transistors operate in linear region in active mode. VDD VGND GND I(ST) I(ST): the current through the sleep transistor V ST V ST : the voltage drop across the sleep transistor

38 38 Sleep Transistor (ST) Sizing Determine the minimum required size (W ST * ) based on: Determine the minimum required size (W ST * ) based on: 1.MIC(ST) 2.V ST *: IR-drop constraint VDD VGND GND MIC(ST) MIC(ST) : Maximum Instantaneous Current (MIC) through ST Smaller MIC(ST) leads to a better ST size!

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