1. The MAD chip: 4 channel preamplifier + discriminator

3. The MAD-Chip Board En/Disabling channels over I2C bus (Philips PCF8577) MAD Chips Example shown here: 16 channel Frontend Board (INFN Italy) Input for test signal 16 chan output (LVDS->TDC) Threshold Setting Temperature Readout Front Side Front side of board Test points

4. The MAD-Chip Board Example shown here: 16 channel Frontend Board (INFN Italy) Back Side Input for test signal Differential wire signal inputs (as close to MAD chips as possible) Back side of board

5. 16 channel output Connector (LVDS) 8 channel input connector 8 channel input connector I2C Channel Control (backside?) MAD Chip INFN Layout (154x44 mm) Qweak possible Layout Connection to Ground bar (+ Mounting Holes) Daisy Chain I2C Bus Input for test signal

6. Principle of a traditional delayline readout Example for a delayline readout with an interleave factor Fi=3 and N=4 Total number of TDC channel needed for delayline readout (2x Dual VDC chambers) #chan = 2*FI*Nplanes with FI=8 = 2*8*8 = 128 channels (=64/Octant) -> 256 channels (Top/Bottom RO) Qweak Parameters: FI =8 (Interleave Factor) Tau =1ns or less, (depends only on TDC resolution and signal jitter ) N=18 (top/bottom Readout) Max Deadtime: N*Tau ~18ns ( 1 Channel of MAD chip)

7. 8 TDC channels “Top readout” of 141 wires “Bottom readout” of 141 wires Principle of the Encoding Readout System (EROS) 8 x 5-Bit Bus for decoding the channel number (8*2^5 = 256 max) To Pattern Logic (40 channels) To Pattern Logic (40 channels) 282 wires per plane, Read out by 16 TDC channels and a 2*256 Pattern Unit. (VDC: Max 8 simultaneous wire hits per track) Channel Bit Pattern (2^5 =32) -> Delayline free readout (less dead time) Preamplifier/ Discriminator (MAD Board)

8. Total amount of 16-chan boards: 18x2 x4 = 144, say 150 including spares (18 boards per wire plane (9 for top readout, 9 for bottom readout), 2 wire planes per wire chamber, 4 wire chambers in total)

11. Current Redesign of Flexible Interface Board (W&M task) -Based on Bill Gunning’s design - Modified based on feedback from several FlexBoard companies () - Coverlayers: Surface Mount Access, Hold-Down Tabs, Pad Fillets for preventing peel-offs

12. Design requirements: A) Total number of preamplifier circuit boards : 150 (min. 144) B) MAD chip control 1) Individual channel disable: yes 2) Threshold control per chip or per board? Per board 3) Output pulse width fixed or adjustable? Default: fixed (we have to figure out the value) 4) External logic for trigger? No C) I^2C control functions see next slides 1) Calibration test input required? Yes, like in BigBite (capacitive coupling of a test signal trace to the input traces. Test signal trace should be terminated with 50 Ohms ) 2) Flexible boards to interface chamber wires to readout cards Will be done by W&M (CAD drawings) 3) Interface Flexible Board to Preamplifier: to be (re)defined (Task of W&M) D) HV bias distribution circuits? No E) Any other design considerations for interfacing the MAD chip outputs to standard readout electronics?{TDC etc.} -Depending on the TDC: LVDS to ECL translator cards (16x 16channel cards) -Smarter: Remove the ECL->LVDS converter of F1-TDC, use LVDS directly

13. Shown is the scheme for controlling a single 16 channel front-end board using I2C chips. PCF 8575 is used for disabling or enabling the MAD chip inputs individually. PCF 8591 is used for monitoring the regulated voltages + applied threshold (4x 8 Bit ADC) and for setting the threshold per board (1x 8 BitADC). The threshold voltage from the ADC will be divided by e.g. 20 using a passive divider chain (e.g. 5V == 250mV actual threshold, step ~1mV) Wire signal Output is LVDS, will be hooked up to a remote LVDS->ECL translator board Front-End I2C Control MAD #1 MAD #2 MAD #3 MAD #4 input con. 1 6 I / O P C F 8 5 7 5 4x ADC 1x DAC PCF 8591 Voltage Regulators (+5,+2.5,+1.5) I2C 16 chan output

14. This is a draft of how to address the I2C chips on each Frontend Electronics board (FE) that commonly have a limited address identifier of 3 Bits (8 different ID’s of the same kind of chip) using I2C multiplexer. The shown multiplexing scheme is for one drift chamber consisting of 2 wire planes (U,V).

15. The Qweak Region 3 Rotator Drift Chamber #1, #2 Drift Chamber #3, #4 Sliding arms, rigid unit with drift chambers The rotator allows to rotate the drift chambers around the beam line.In addition the drift chambers are mounted on sliding arms that allow a radial movement. It would be best to mount the LVDS->ECL converter and the delay line board on the sliding arms (to the left or right of a drift chamber).

16. Suggested location of converter and delayline boards Drift chamber front panel with LVDS output connectors

17. Some W&M studies with a 16 channel MAD chip based board

18. Front-End Electronics 1 C LVDS OUT Threshold (common) Pulse Generator 2 3 4 1 2 3 4 4 Channel MAD Chip scaler Charge Sensitivity INFN: 3.77 fC/mV +- 5% W&M: 3.97 fC/mV +- 2% Preliminary Crosstalk Studies Adjacent Channels: max. 1-2 ppm

19. Using small pulses at the rate of 500kHz, tests were performed to determine the useful range of the MAD chip, dependent upon the threshold. A threshold of approximately 8.0-10.0mV is the lower limit before noise overwhelms the system. All inputs were perfomed on Channel 5 with a 1pF SMD capacitor replacing the 0.1uF capacitor. Significant cross talk: 1 or more out of 10.000 input pulses on chan #5 triggered any other channel (with no input)