1. 1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)

2. 2 Contents Logic Synthesis into the Balsa flow  Design flow  Structural methods to fight the state explosion  Structural Clustering based on Petri nets composition Experimental Results

3. 3 Logic Synthesis into the Balsa System

4. 4 Design flow Cluster HCs

5. 5 Describe Behavior Design flow | ;

6. 6 Compose STGs Design flow | | ; ; |

7. 7 Hide Internals Design flow

8. 8 State Explosion Problem Enumerate States Design flow PETRI NET STATE GRAPH

9. 9 Contents Logic Synthesis into the Balsa flow  Design flow  Structural methods to fight the state explosion  Structural Clustering based on Petri nets composition Experimental Results

10. 10 Structural Methods Solve CSC (Moebius [Carmona et al. 2006]) MILP formulation: MILP “s=0 implicit” MILP “s=1 implicit” #( σ 1,s+) = #( σ 1,s-) + 1 #( σ 2,s-) = #( σ 2,s+) + 1 M 0 [s=0] + M 0 [s=1] = 1

11. 11 Structural Methods Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies

12. 12 Enumerate States Structural Methods PETRI NETSTATE GRAPH

13. 13 Synthesize (Petrify [Cortadella et al. 1996]) Structural Methods ack_16 = csc_2' csc_3' csc_1' LOGIC EQUATION (ack_16)

14. 14 Contents Logic Synthesis into the Balsa flow  Design flow  Structural methods to fight the state explosion  Structural Clustering based on Petri nets composition Experimental Results

15. 15 Clustering Techniques Cluster HCs

16. 16 Clustering Techniques Cluster HCs

17. 17 Describe Behavior Clustering Techniques Complex STG

18. 18 Structural Clustering Techniques Well-structured Petri net subclasses: State machine (SM), Marked Graph (MG), Free-choice (FC) and Asymmetric choice (AC) Idea: well-structured STGs will be obtained if the growth of cluster is bounded by one of these subclasses

19. 19 Structural Clustering Techniques PN Class of Synchronization Area

20. 20 Structural Clustering Techniques PN Class of HC Connection

21. 21 Clustering Techniques Cluster HCs

22. 22 Clustering Techniques Cluster HCs

23. 23 Clustering Techniques Describe Behavior

24. 24 Experimental Results

25. 25 Conclusions Structural Clustering Techniques To Avoid complex STGs To Fulfill Structural Properties Safe Logic Synthesis Balsa [Edwards et al. 2002] Moebius [Carmona et al. 2006] Petrify [Cortadella et al. 1996] Structural Clustering Techniques [Fernández-Nogueira et al. 2008] Logic Synthesis into the Balsa System + + +

26. 26 Conclusions The design of async circuits cannot be faced without the help of CAD tools. This work is an example where the theory of Petri nets helps for optimizing async circuits. Advocate for interdisciplinary research. Future Work:  Other optimization goals: energy consumption.  Specification of more HCs Paper at PATMOS’08

27. 27 Thank You! Are There Any Questions?

28. 28 Solve CSC (Petrify [Cortadella et al. 1996]) Logic Synthesis of async controllers

29. 29 Project into Signal Support (Moebius [Carmona et al. 2006]) + Structural Methods

30. 30 + Structural Methods Enumerate States State Explosion Problem

31. 31 + Structural Methods Enumerate States State Explosion Problem

32. 32 Project into Signal Support (Moebius [Carmona et al. 2006]) + Delete Dummies + Structural Methods

33. TRASH SLIDES

34. 34 Introduction: asynchronous D1D1 D2D2 DNDN inout... clock t1t1 t2t2 t N-1 L1L1 L2L2 LNLN inout... C1C1 C2C2 CNCN t1t1 t2t2 t N-1 Asynchronous Advantages: High Performance Low Power Dissipation Low Noise and Low Electromagnetic Emission A Good Match with Heterogeneous System Timing...

35. 35 Structural Methods Solve CSC (Moebius [Carmona et al. 2006]) MILP formulation: MILP “s=0 implicit” MILP “s=1 implicit” #( σ 1,s+) = #( σ 1,s-) + 1 #( σ 2,s-) = #( σ 2,s+) + 1 M 0 [s=0] + M 0 [s=1] = 1

36. 36 Related Work Assassin [Ykman-Couvreur et al. 1994] Minimalist [Fuhrer et al. 1999] Petrify [Cortadella et al. 1996] Moebius [Carmona et al. 2006] Tangram [van Berkel et al. 1999] Balsa [Edwards et al. 2002] Tangram+Assassin [Kolks et al. 1996] Balsa+Minimalist [Chelcea et al. 2002] Tangram+Petrify [Peña et al. 1996] Balsa+Moebius+Petrify [Fernández-Nogueira et al. 2008] Signal Transition Graphs Handshake Components State Based Methods Structural Methods CLP [Khomenko et al. 2002] Burst-mode Finite-state Machines Unfolding Methods DesiJ [Schaefer & Vogler. 2007] CSAT [Khomenko et al. 2003]

37. 37 Introduction Moore's LawSystem on a Chip

38. 38 Delete Dummies Design flow

39. 39 Synchronization Area Structural Clustering Techniques

40. 40 PN Class of Synchronization Area Structural Clustering Techniques

41. Introduction As it becomes impossible to move signal across a large die within one clock cycle, the likely result is a shift to asynchronous design style “As it becomes impossible to move signal across a large die within one clock cycle, the likely result is a shift to asynchronous design style”. International Technology Roadmap for Semiconductors (ITRS 2001) Intel Pentium IV (47M transistors)

42. 42 Summary of problems for shifting to asynchronous  Asynchronous circuits are difficult to design, need for CAD tools.  Most of the dominant CAD tools for asynchronous synthesis suffer from the state explosion problem.  If asynchronous HDLs are used, the derived circuits are unoptimized, in terms of area and speed.

43. 43 Contents Introduction Synthesis of async circuits  VLSI programming  Logic synthesis Logic Synthesis into the Balsa flow  Design flow  Structural methods to fight the state explosion  Structural Clustering based on Petri nets composition Experimental Results

44. 44 Asynchronous Hardware Description Languages (a?byte & b!byte) begin x0: var byte | forever do a?x0 ; b!x0 od end Buffer * x a b T ; T a b passive port active port Data path Each circle mapped to a netlist FF x not x li lo ri ro

45. 45 Syntax-directed Translation procedure buffer2 (input i1,i2 : byte; output o1,o2 : byte;) is variable x1,x2 : byte; begin loop i1 -> x1 || i2 -> x2 ; o1 <- x1 || o2 <- x2 end Balsa [Edwards et al. 2002] Asynchronous Hardware Description Languages

46. 46 Contents Introduction Synthesis of async circuits  VLSI programming  Logic synthesis Logic Synthesis into the Balsa flow  Design flow  Structural methods to fight the state explosion  Structural Clustering based on Petri nets composition Experimental Results

47. 47 Logic Synthesis of async controllers DSr LDTACK LDS DTACK D VME Bus Controller Device DSw Data Transceiver Bus Describe Behavior PETRI NET

48. 48 Enumerate States Complete State Coding Conflicts Logic Synthesis of async controllers PETRI NET STATE GRAPH

49. 49 Logic Synthesis of async controllers Solve CSC (Petrify [Cortadella et al. 1996])

50. 50 Synthesize (Petrify [Cortadella et al. 1996]) lds = csc0 + d d = ldtack csc0 dtack = d csc0 = dsr (csc0 + ldtack') Logic Synthesis of async controllers LOGIC EQUATIONS