1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 426 - VLSI System Design Lecture 10 - Communicating ASMs March 3, 2003

2. 3/3/03Lecture 10 - Handshaking2 Where we are...  Last Time  ASM Diagrams  Discuss Lab 5  Today - Register Transfer Design  Handshaking  FIFOs

3. 3/3/03Lecture 10 - Handshaking3 Handshaking  Basic Idea:  Receiver performs “action” at request of sender Transfer data Perform a sub-computation  Want action to be performed once for each request  Types of Handshaking  1-way  2-way  3-way  4-way (fully interlocked)

4. 3/3/03Lecture 10 - Handshaking4 Goals of Handshaking  Reliably Pass Control Information between ASMs  Reliably Pass Data Between Interacting ASMs  ASMs may be driven by different clocks! SR SR DO_CMD DATA clk1clk2 clk1clk2

5. 3/3/03Lecture 10 - Handshaking5 1-Way Handshake  R waits for CMD before starting action  S asserts CMD to start action CMD SR SCMD S1 SN-2 SN-1 SN SN-1 RWAIT CMD CLK S State R State SN RWAIT SCMD RWAIT S1 R1 S2 R2 CMD RWAIT R1 RM T F

6. 3/3/03Lecture 10 - Handshaking6 1-way Handshake: Observations  Not reliable - why?  Receiver can “miss” assertion of CMD if it isn’t in RWAIT  Receiver may see assertion of CMD twice if it runs on a faster clock than sender

7. 3/3/03Lecture 10 - Handshaking7 2-Way Handshake 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK CMD SR ACK CMD SCMD F SN-2 SN-1 SN ACK CMD RWAIT R1 RM F T ACK SN-1 RWAIT SN RWAIT SCMD RWAIT SCMD R1 S1 R2 CMD CLK S State R State ACK

8. 3/3/03Lecture 10 - Handshaking8 2 Way Handshake - Observations  Reliable if S and R use same clock  Not reliable if S and R use different clocks  R could see CMD twice if R faster than S  S could see ACK twice if S faster than R

9. 3/3/03Lecture 10 - Handshaking9 3-Way Handshake 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK 3.Receiver waits for CMD=0 before continuing CMD SR ACK CMD SCMD F SN-2 SN ACK CMD RW1 RW2 R1 F T ACK SN RWAIT SCMD RW1 CMD CLK S State R State ACK T T F CMD CMD’ SCMD RW2 S1 S2 R1

10. 3/3/03Lecture 10 - Handshaking10 3-Way Handshake - Comments  Use in some asynchronous bus interfaces  Not reliable if S is faster than R (see ACK twice)

11. 3/3/03Lecture 10 - Handshaking11 4-Way Handshake (Fully Interlocked) 1.Sender asserts CMD and waits for ACK before continuing 2.Receiver waits for CMD and then asserts ACK 3.Receiver waits for CMD=0 before continuing 4. Sender waits for ACK=0 before continuing CMD SR ACK RW1 RW2 SC1 RW1 CMD CLK S State R State ACK CMD R1 F T ACK T F CMD CMD’ SC1 RW2 SC2 R1 CMD SC1 F SN ACK T SC2 ACK T ACK’

12. 3/3/03Lecture 10 - Handshaking12 4-Way Handshaking  Works under all circumstances  Still need synchronizers if clocks are different! clk1 clk2 SR CMD ACK clk1 clk2

13. 3/3/03Lecture 10 - Handshaking13 Handshaking with Multiple Clocks  CMD, ACK must be synchronized!  Penalty: even more latency! S R CMD ACK.s1 DQDQ QDQD CMD.s2 ACK clk1clk2

14. 3/3/03Lecture 10 - Handshaking14 Handshaking ASMs with Different Clocks  Treat signals passing between S and R as asynchronous!  Important: never try to handshake on multiple bits  Use synchronizers when crossing clock domains

15. 3/3/03Lecture 10 - Handshaking15 Alternative to Handshaking: FIFOs  FIFO = First In / First Out Buffer  S writes data once each clock cycle unless FULL  R reads data once every clock cycle unless EMPTY SR SCLK FULL RCLK EMPTY

16. 3/3/03Lecture 10 - Handshaking16 FIFO Implementation - Software  Head pointer - marks where to add data  Tail pointer - marks where to remove data  Exceptional conditions: FULL, EMPTY Write Pointer (Head) FULL Head Pointer EMPTY 9 7 5 Array (RAM) 0x0 0x7

17. 3/3/03Lecture 10 - Handshaking17 FIFO Implementation - Hardware Dual-Port RAM WDATA WADDR WR RDATA RADDR Write Logic Read Logic CLK2CLK1 FULL DATA EMPTY DATA  Q: How do we calculate FULL & EMPTY? HEADTAIL

18. 3/3/03Lecture 10 - Handshaking18 FIFO Implementation - Hardware Dual-Port RAM WDATA WADDR WR RDATA RADDR Write Logic Read Logic CLK2CLK1 FULL DATA EMPTY DATA  Q: How do we calculate FULL & EMPTY?  A: Must compare head & tail pointers HEADTAIL

19. 3/3/03Lecture 10 - Handshaking19 FIFO Implementation - Hardware  Problem:  Read logic (clk1) needs to see Tail pointer (clk2)  Write logic (clk2) needs to see the Head pointer (clk1)  Proposed Solution:  Synchronize Head, Tail  Problem again! Multiple bits in Head, Tail  Synchronization won’t work on multiple bits!  Complete Solution:  Use Gray Code for Head, Tail (only 1 bit changes at a time!)  Translate to/from binary internally

20. 3/3/03Lecture 10 - Handshaking20 Coming Up  Timing w/ Design Compiler  Discuss Project

21. 3/3/03Lecture 10 - Handshaking21 Alternative - Buffering with a FIFO  FIFO = First in First Out Buffer

22. 3/3/03Lecture 10 - Handshaking22 Synchronization Problems

23. 3/3/03Lecture 10 - Handshaking23 Coming Up:  Multiple Controller / Datapath Designs  Synchronization Issues with Multiple Controllers

24. 3/3/03Lecture 10 - Handshaking24 Verification Plan  Definition: A Specification of the Verification Effort  Prerequisite: Specification document for design  Defnining Success - Must Identify  Features which must be exercisedunder which conditions  Expected Response

25. 3/3/03Lecture 10 - Handshaking25 Levels of Verification  Board  System / Subsystem  ASIC / FPGA  Unit / Subunit

26. 3/3/03Lecture 10 - Handshaking26 Levels of Verification  Connectivity  Transaction / Cooperative Data Flow  Functionality  Ad Hoc  Designer verifies basic functionality

27. 3/3/03Lecture 10 - Handshaking27 Levels of Verification - Notes  Stable interfaces required at each level of granularity

28. 3/3/03Lecture 10 - Handshaking28 System Design Issues  ASM Diagrams  Synchronization & Metastability  Handshaking  Working with Multiple Clocks

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