Chapter 4: The Embedded Computing Platform

Name: Chapter 4: The Embedded Computing Platform
Uploaded: 2017-07-26T15:34:39+00:00
Duration: PTM34S2
Channel: Sydnie McAllister
Description: Chapter 4: The Embedded Computing Platform

Chapter 4: The Embedded Computing Platform
Computer as Components Embedded Systems Laboratory Dept. of Computer Science & Engineering National Sun Yat-Sen University Presenter: Chung-Fu Kao

The Embedded Computing System© C.-F. Kao
Chapter view CPU bus, I/O devices, and interfacing The CPU system as a framework for understanding design methodology Development environments and debugging An alarm clock design The Embedded Computing System© C.-F. Kao 4/9/2002

Typical PC hardware platform
CPU memory device CPU bus interface bus high-speed bus DMA controller intr ctrl timers low-speed bus bus interface device The Embedded Computing System© C.-F. Kao 4/9/2002

Introduction Computer platform Microprocessors I/O devices Memory How to interconnect microprocessors and devices using the CPU bus device ? keyboard CPU device display device memory The Embedded Computing System© C.-F. Kao 4/9/2002

The CPU bus Wire vs. bus Wire: a 1-bit line between two devices Bus: a collection of wires with a protocol wire n bus The Embedded Computing System© C.-F. Kao 4/9/2002

Bus protocol The simplest bus protocol is the four-cycle handshake Action enq 1 2 3 4 data ack time The Embedded Computing System© C.-F. Kao 4/9/2002

Typical bus signals Clock provides synchronization to the bus components R/W’ true when bus is reading Address a n1-bit bundle Data a n2-bit bundle Data ready’ The Embedded Computing System© C.-F. Kao 4/9/2002

A typical microprocessor bus
the CPU can read/write devices or memory, bus devices of memory cannot initiate a transfer CPU Device 1 memory clock R/W’ data rdy’ address data The Embedded Computing System© C.-F. Kao 4/9/2002

Timing diagrams zero one 10 ns A rising falling B stable changing Timing constraint C time The Embedded Computing System© C.-F. Kao 4/9/2002

A simple transfer example
The Embedded Computing System© C.-F. Kao 4/9/2002

Transfer with ‘wait’ states

State diagrams for the bus read transaction
Get data Done Send data Release ack See ack ack Address (start here) Address (start here) Wait Wait CPU Device The Embedded Computing System© C.-F. Kao 4/9/2002

Bus read state diagram Get data Done Address (start here) Wait See ack one data send/receive per transfer cycle How to speedup the transfer ? The Embedded Computing System© C.-F. Kao 4/9/2002

Burst transfer The Embedded Computing System© C.-F. Kao 4/9/2002

Bus architectures: Tri-state design
1-bit tri-state design System tri-state bus enable data_out data_in tri_out … The Embedded Computing System© C.-F. Kao 4/9/2002

Bus architectures: Multiplexing design
End of Chapter 4.2.1 The Embedded Computing System© C.-F. Kao 4/9/2002

I/O techniques Programmed I/O data are exchanged between CPU and I/O CPU must wait until the I/O operation is complete Interrupt-driven I/O CPU can continues to execute other instructions before I/O operation has completed Direct Memory Access (DMA) CPU does not involve the I/O transfer The Embedded Computing System© C.-F. Kao 4/9/2002

DMA: Direct Memory Access
The DMA controller includes 3 registers a starting address register a length register a status register Cycle stealing Data count Data register Address register Control Logic DMA REQ INTR DMA ACK Read Write The Embedded Computing System© C.-F. Kao 4/9/2002

Possible DMA configuration

Bus example: ARM bus ARM supports an on-chip bus: AMBA Advanced Microcontroller Bus Architecture Arbiter BIU: Bus Interface Unit Master BIU CPU Master BIU Master N Slave BIU Other APB slaves Slave BIU Timer …… APB Bridge AHB/ASB BUS APB BUS Interrupt Controller Slave BIU LED Slave BIU On-chip RAM Decoder The Embedded Computing System© C.-F. Kao 4/9/2002

AMBA features Pipelining only AHB or ASB Burst transfers 1, 4, 8, 16-beat transfer Split transactions release the current transfer Multiple bus masters The Embedded Computing System© C.-F. Kao 4/9/2002

Bus components devices
Arbiter BIU: Bus Interface Unit Master BIU CPU Master BIU Master N Slave BIU Other APB slaves Slave BIU Timer …… APB Bridge AHB/ASB BUS APB BUS Interrupt Controller Slave BIU LED Slave BIU On-chip RAM Decoder The Embedded Computing System© C.-F. Kao 4/9/2002

Memory device organization
The most basic way to characterize a memory is by its capacity A 4-Mbit memory aspect ratio : as a 1M x 4-bit array, MAX of 220 different addresses as a 4M x 1-bit array, MAX of 222 different addresses The Embedded Computing System© C.-F. Kao 4/9/2002

Random-Access Memories (RAMs)
There are two major categories of RAM: static RAM (SRAM) dynamic RAM (DRAM) The differences between SRAM and DRAM SRAM is faster than DRAM SRAM consumes more power than DRAM more DRAM can be put on a single chip DRAM values must be periodically refreshed The Embedded Computing System© C.-F. Kao 4/9/2002

SRAM SRAM doesn’t need CLOCK signal Block diagram Timing diagram SRAM 32K x 8 address chip select output enable write enable Data_in Data_out 15 8 CS’ R/W’ Adrs Data From SRAM From CPU The Embedded Computing System© C.-F. Kao 4/9/2002

DRAM Single transistor and capacitor per bit CPU address bus is split into a row and a column address NO clock Refreshed CAS-before-RAS refresh DRAM address chip select output enable write enable Data_in Data_out 15 8 The Embedded Computing System© C.-F. Kao 4/9/2002

Other DRAMs FPM DRAM fast page mode switch (burst) EDO DRAM extended data out SDRAM synchronous DRAM The Embedded Computing System© C.-F. Kao 4/9/2002

Read-Only Memories (ROMs)
Read only, cannot write any data to ROMs ROMs can store data without any power ROM size height: n input line, consists 2n addressable entries width: the number of bits in each addressable entry A ROM can encode a collection of logic functions directly from the truth table The Embedded Computing System© C.-F. Kao 4/9/2002

ROMs Mask ROM Programmable ROM (PROM) write once Erasable Programmable ROM (EPROM) can be erased using UV light and then reprogrammed Electrically Erasable Programmable ROM using high voltages for erasure and reprogramming Flash ROM The Embedded Computing System© C.-F. Kao 4/9/2002

I/O devices Timers / counters A/D and D/A converters Keyboards LEDs Displays Touchscreens The Embedded Computing System© C.-F. Kao 4/9/2002

Timers and counters Very similar: a timer is incremented by a periodic signal a counter is incremented by an asynchronous, occasional signal Rollover causes interrupt The Embedded Computing System© C.-F. Kao 4/9/2002

Watchdog timer Watchdog timer is periodically reset by system timer If watchdog is not reset, it generates an interrupt to reset the host (CPU) reset time-out CPU Watchdog Timer The Embedded Computing System© C.-F. Kao 4/9/2002

A/D and D/A converters Analog/digital (A/D) or digital/analog (D/A) converters (ADC/DAC) To interface non-digital devices to embedded systems A typical A/D interface has two major digital inputs a data port a clock input The Embedded Computing System© C.-F. Kao 4/9/2002

DAC The Embedded Computing System© C.-F. Kao 4/9/2002

ADC The Embedded Computing System© C.-F. Kao 4/9/2002

Keyboards Switch de-bouncing Encoded keyboard An array of switches is read by an encoder row The Embedded Computing System© C.-F. Kao 4/9/2002

LEDs Light-emitting diodes (LEDs) + +5 V Anode (+) Cathode (-) The Embedded Computing System© C.-F. Kao 4/9/2002

Displays Common use: 7-segment LCD display Other high-resolution displays cathode ray tube (CRT) liquid crystal display (LCD) passive matrix active matrix The Embedded Computing System© C.-F. Kao 4/9/2002

Touchscreens Includes input and output device Input device is a two-dimensional voltmeter X The Embedded Computing System© C.-F. Kao 4/9/2002

Touchscreen position sensing
voltage Push ↓ ADC conductive sheets spacer ball end of chapter 4.5 The Embedded Computing System© C.-F. Kao 4/9/2002

Design with microprocessors
System architecture Hardware design The PC as a platform Debugging Manufacturing testing The Embedded Computing System© C.-F. Kao 4/9/2002

System architecture – Hardware
Hardware elements CPU bus memory I/O devices: networking, sensors, etc. The Embedded Computing System© C.-F. Kao 4/9/2002

System architecture – Software
Functional description must be broken into pieces: conceptual organization performance testability maintenance Consider the H/W-S/W trade-off using DMA to move data rather than a programmed loop The Embedded Computing System© C.-F. Kao 4/9/2002

Hardware design Hardware: evaluation board Software: cross compiler: compiles code on host for target system. cross debugger: displays target state, allows target system to be controlled. target system host system serial line The Embedded Computing System© C.-F. Kao 4/9/2002

Evaluation board The Embedded Computing System© C.-F. Kao 4/9/2002

The PC as a platform Advantages: cheap and easy to get rich and familiar software environment Disadvantages: requires a lot of hardware resources not well-adapted to real-time high power consumption The Embedded Computing System© C.-F. Kao 4/9/2002

Typical PC hardware platform
CPU memory device CPU bus interface bus high-speed bus DMA controller intr ctrl timers low-speed bus bus interface device The Embedded Computing System© C.-F. Kao 4/9/2002

Typical busses ISA (Industry Standard Architecture) original IBM PC bus, low-speed by today’s standard. PCI (Peripheral Component Interconnect) standard for high-speed interfacing 33 or 66 MHz. USB (Universal Serial Bus), IEEE 1394 (Firewire) relatively low-cost serial interface with high speed. The Embedded Computing System© C.-F. Kao 4/9/2002

Software elements IBM PC uses BIOS (Basic I/O System) to implement low-level functions: boot-up minimal device drivers BIOS has become a generic term for the lowest-level system software The Embedded Computing System© C.-F. Kao 4/9/2002

Debugging embedded systems
Challenges: target system may be hard to observe target may be hard to control may be hard to generate realistic inputs setup sequence may be complex The Embedded Computing System© C.-F. Kao 4/9/2002

Software debuggers A monitor program residing on the target provides basic debugger functions Debugger should have a minimal footprint in memory User program must be careful not to destroy debugger program, but , should be able to recover from some damage caused by user code The Embedded Computing System© C.-F. Kao 4/9/2002

Breakpoints A breakpoint allows the user to stop execution, examine system state, and change state Replace the breakpointed instruction with a subroutine call to the monitor program The Embedded Computing System© C.-F. Kao 4/9/2002

ARM breakpoints 0x400 MUL r4,r6,r6 0x404 ADD r2,r2,r4 0x408 ADD r0,r0,#1 0x40c B loop uninstrumented code 0x400 MUL r4,r6,r6 0x404 ADD r2,r2,r4 0x408 ADD r0,r0,#1 0x40c BL bkpoint code with breakpoint The Embedded Computing System© C.-F. Kao 4/9/2002

Breakpoint handler actions
Save registers Allow user to examine machine Before returning, restore system state safest way to execute the instruction is to replace it and execute in place put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint (pp ) The Embedded Computing System© C.-F. Kao 4/9/2002

In-circuit emulators A microprocessor in-circuit emulator is a specially-instrumented microprocessor Allows you to stop execution, examine CPU state, modify registers The Embedded Computing System© C.-F. Kao 4/9/2002

Logic analyzers A logic analyzer is an array of low-grade oscilloscopes: The Embedded Computing System© C.-F. Kao 4/9/2002

Manufacturing testing
Goal: ensure that manufacturing produces defect-free copies of the design Can test by comparing unit being tested to the expected behavior but running tests is expensive Maximize confidence while minimizing testing cost The Embedded Computing System© C.-F. Kao 4/9/2002

Testing concepts Yield: proportion of manufactured systems that work proper manufacturing maximizes yield proper testing accurately estimates yield Field return: defective unit that leaves the factory. The Embedded Computing System© C.-F. Kao 4/9/2002

Faults Manufacturing problems can be caused by many thing Fault model: model that predicts effects of a particular type of fault Fault coverage: proportion of possible faults found by a set of test having a fault model allows us to determine fault coverage The Embedded Computing System© C.-F. Kao 4/9/2002

Software vs. hardware testing
When testing code, we have no fault model we verify the implementation, not the manufacturing simple tests work well to verify software manufacturing Hardware requires manufacturing tests in addition to implementation verification The Embedded Computing System© C.-F. Kao 4/9/2002

Hardware fault models Stuck-at 0/1 fault model: output of gate is always 0/1 1 The Embedded Computing System© C.-F. Kao 4/9/2002

Combinational testing
Every gate can be stuck-at-0, stuck-at-1 Usually test for single stuck-at-faults one fault at a time multiple faults can mask each other We can generate a test for a gate by: controlling the gate’s input observing the gate’s output through other gates The Embedded Computing System© C.-F. Kao 4/9/2002

Sequential testing A state machine is combinational logic + registers Sequential testing is considerably harder a single stuck-at fault affects the machine on every cycle fault behavior on one cycle can be masked by same fault on other cycles The Embedded Computing System© C.-F. Kao 4/9/2002

Scan chains A scannable register operates in two modes: normal scan forms an element in a shift register The Embedded Computing System© C.-F. Kao 4/9/2002

Scan chain cell EXTEST INTEST Scan output SEL MUX Input pin Input signal to logic scan SEL MUX BSR PDR Shift clock Update clock Scan input The Embedded Computing System© C.-F. Kao 4/9/2002

Boundary scan IEEE Std JTAG boundary scan Serial data in Serial data out Serial test interconnect System interconnect The Embedded Computing System© C.-F. Kao 4/9/2002

Chapter 4: The Embedded Computing Platform

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