1. Changes in input values are reflected immediately (subject to the speed of light and electrical delays) on the outputs Each gate has an associated “electrical delay” Delays are often ignored for the purpose of the logic design (but not for the real implementation!) As soon as inputs change, the outputs change – no memory of what happened before  (at least conceptually) Combinational Logic

2. Latches & Flip-Flops

3. Example Needing Bit Storage Flight attendant call button  Press call: light turns on Stays on after button released  Press cancel: light turns off  Logic gate circuit to implement this? Q Call Cancel Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0 Need some form of “feedback” in the circuit a a Bit Storage Blue light Call button Cancel button 1. Call button pressed – light turns on Bit Storage Blue light Call button Cancel button 2. Call button released – light stays on Bit Storage Blue light Call button Cancel button 3. Cancel button pressed – light turns off

4. First attempt at Bit Storage We need some sort of feedback  Does circuit on the right do what we want? No: Once Q becomes 1 (when S=1), Q stays 1 forever – no value of S can bring Q back to 0 Q S t 1 0 1 0 1 0 Q t S 0 t 1 Q S 0 0 t 1 Q S 1 1 t 1 Q S 1 1 t 0 Q S 1

5. Basic NOR (SR) Latch When Set = 0, Reset = 1  Q = 0 When Set = 1, Reset = 0  Q = 1 When Set = Reset = 0  Q = memory When Set = Reset = 1  Q = 0 Reset SetQ

6. Basic NOR Latch Redrawn Q Q R S SRQQ 000/11/0 0101 1010 1100 memory state

7. Timing Analysis of Basic Latch  What happens at t 10 ?? S and R both go from 1 to 0 simultaneously If gate delays are exactly the same  oscillation!!! 1 0 1 0 1 0 1 0 R S Q Q ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 Q Q R S

8. Gated SR Latch  To get better control of the state changes, we must limit when the input signals affect the outputs  Outputs change only when Clk = 1 Clk acts as an Enable signal Q Q R S Clk SRQ(t+1) 0xxQ(t) 100 1010 1101 111x undefined since we don't know which stable state will result

9. Comments on Latches  Need to avoid the unstable state Note that all other states have “correct” Q and Q  Can use the cross-coupled NOR approach, or can use the cross-coupled NAND approach All gates are the same type S R Clk Q Q S Q Q R

10. Gated D Latch  Provide only a single control signal D (for Data) More common than SR latch, and simpler Q S R Clk D (Data) Q ClkDQ(t+1) 0xQ(t) 100 111 D Q QClk

11. D Latch Timing Diagram  Output Q changes only when Clk = 1 Q tracks D when Clk = 1  This latch is level-sensitive since the output is sensitive to the level of the clock t 1 t 2 t 3 t 4 Time Clk D Q

12. Master-Slave D Flip-Flop  Desire to remove the level-sensitive nature Want changes in Q only on the transition of the Clk signal from 1  0 (or from 0  1) When Clock = 1, master D latch tracks D; slave D latch remains unchanged (Q remains fixed) When Clock = 0, master D latch is unchanged; slave D latch tracks Q m D Q Q MasterSlave D Clock Q Q D Q Q Q Clk D Q Q negative edge-triggered flip-flop

13. Timing of Master-Slave D Flip-Flop Changes to Q occur only on the negative edge of the Clock D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk D Clock Q m QQ s =

14. Terms, Reviewed  Latch Two NANDs (or NORs) used to store one bit  Gated latch Latch with an control enable, called Clk Two basic types: SR and D, both level sensitive  Master-slave flip-flop State changes only on clock edge; made from two gated D latches

15. Registers  A flip-flop stores one bit of information  When you want to store n bits  register n flip-flops used Clock is shared by all so action is synchronous with clock edge  Some common register types Simple register Shift register Parallel access shift register Lots of counters: up counter, down counter, BCD counter, ring counter, Johnson counter

16. Simple 4-bit Register  A standard 4 bit register using D flip flops Q 3 Q 2 Q 1 Q 0 Clock Parallel input Parallel output D Q Q D Q Q D Q Q D Q Q

17. 4-bit Register with Load Control  Controlling the load capability Q 3 Q 2 Q 1 Q 0 Clock Parallel input Parallel output D Q Q D Q Q D Q Q D Q Q Load