1. A Robust, Fast Pulsed Flip- Flop Design By: Arunprasad Venkatraman Rajesh Garg Sunil Khatri Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX

2. Introduction High speed VLSI design uses heavy pipelining –Results in increased number of Flip-Flops For mobile devices –Power consumption is the prime concern –Requires low power Flip-Flops –Also demand for high speed operation Hence there is a strong need for Flip Flops with: –High speed –Low power –Low area –Tolerance to PVT variations

3. Figure of Merit - Timing Time period T ≥ T cq + T su +  where  – delay of the combinational circuit T su – setup time of the Flip-Flop T cq – clock to Q delay of the Flip-Flop So T cq + T su is the required figure of merit of the FF, since  is circuit-dependent

4. Traditional Flip-Flops Data needs to arrive before the clock edge –So setup time T su is positive Hence T cq + T su is much higher Want to design a flip-flop with a goal of minimizing the figure of merit T cq + T su We explored different circuit designs with this goal in mind, while ensuring that the resulting flip-flop achieves –Low power and area –High speed –Robustness to PVT variations

5. Pulsed Flip-Flops (P-FF) Broadly: consists of a pulse generator + latch Pulse is derived from clock edge –So pulse is generated after clock edge Hence data can arrive even after the clock edge (therefore T su may be negative) Data Pulse Clk Latch D Clk Q Data Pulse Generator Clk Pulse

6. Proposed Pulsed Flip-Flop The proposed pulse generator design The latch structure

7. Clock falls, node Z is pulled up to VDD Clock rises, N2 discharges internal node W Until W discharges, N2 and N1 helps to discharge Z Very fast slew rates for falling edge of Z Waveforms obtained at various nodes Operation of Pulse Generator

8. Experimental Setup Implemented our Pulse Flip-Flop in BPTM 100nm Compared with other Flip-Flop designs –Explicit Flip-Flop –Improved hybrid pulsed Flip-Flop –Traditional D Flip-Flop Performed Monte Carlo simulations for supply voltage (VDD), channel length (L), threshold voltage (V TH ) variations –500 Monte Carlo simulations –3σ = 10% for VDD, L and V TH

9. Pulsed Flip-Flops Compared Explicit Pulsed Flip-FlopImproved Hybrid latch Flip-Flop

10. FLIP- FLOPS T cq (ps) Power (µW) T su (ps) T hold (ps) T cq + T su (ps) Clock Load (µm 2 ) µσµ  µσµσµσ OUR PULSED FF 95.28.58.71.1-68.811.287.411.226.32.70.11 HYBRID LATCH PULSED FF 11714.78.40.9-34.41.9424.882.611.80.13 EXPLICIT PULSED FF 120.429.314.61.8-54.24.5108.211.665.87.30.05 Traditional D-FF 69.91.57.61.321.42.529.93.191.28.70.09 Experimental Results

11. Proposed Pulsed Flip-Flop Master-Slave D Flip-Flop Layout Comparison Our proposed pulsed Flip-Flop has 27% lesser area than a traditional D Flip-Flop

12. We proposed a novel pulsed Flip-Flop (P-FF) design The performance of our P-FF design is better than other FFs –60% better T cq + T su than other pulsed Flip-Flops –40% lower power dissipation than explicit pulsed Flip-Flop –27% lesser area than a master-slave D Flip-Flop Our P-FF is more robust to process and voltage variations than other designs considered Performed Monte Carlo simulations with varying VDD, L and V TH Our design has the lowest standard deviation of T cq + T su We can further reduce area and power by sharing pulse generator circuit between several latches Conclusions