1. 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU1 Flip Flops Not a gymnastic movement.

2. 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU2 Class 20 – Flip Flops  Definitions  Latches Set-Reset – SR The D Latch  Material from section 5-3 of text

3. Triggers  When the control input to a flip-flop changes value the state of the latch in the flip-flop will change state.  In a D-latch when the control input is a ‘1’, any changes on the input D will propagate to the output with the value of D at the time the control transitions from ‘1’ the final stored value.  In a D flip-flop, the value on D on the rising edge (falling edge) of the control input will be the captured value. 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU3

4. Flip-flops  Constructed in such a way that they are edge- triggered.  This is in contrast to latches which are level sensitive and said to be transparent.  There are two general methodologies for making flip-flops Edge-triggered Master-Slave 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU4

5. Master Slave Flip-flops  The Master-Slave SR Flip-flop  And its operation 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU5

6. Master Slave D Flip-flop  Can be constructed from the MS SR FF by replacing the master SR latch by a D latch.  This arrangement is also negative edge triggered. 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU6

7. A HDL model of the same  The SR latch model with control input C 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU7 ENTITY SR_latch IS PORT (S,R,C : IN BIT; Q, Q_bar : OUT BIT); END SR_latch; ARCHITECTURE one OF SR_latch IS SIGNAL CS,CR : BIT; SIGNAL Q_int, Q_bar_int : BIT; BEGIN CS <= S nand C after 1 ns; CR <= R nand C after 1 ns; Q_int <= CS nand Q_bar_int after 1 ns; Q_bar_int <= CR nand Q_int after 1 ns; Q <= Q_int; Q_bar <= Q_bar_int; END one;

8. A testbench to provide stimulus  tb model  Links in the latch in a master slave manner 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU8

9. VHDL simulation results  Waveform display 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU9

10. The D Flip-flop  The D can be constructed from the use of a D latch and an SR latch. 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU10

11. For a positive edge FF  Add an inverter to the clock input 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU11

12. HDL model and simulation  A HDL model of the D latch was written. 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU12

13. HDL simulation  Results now for the D F/F  Remember the delays 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU13

14. Flip flop with preset and clear 9/15/09 - L20 Flip Flops  Allows direct setting of state of flip-flop.  When initially powered state of flip-flop is unknown. The sets the FF to a known state. Copyright 2009 - Joanne DeGroat, ECE, OSU14

15. Class 20 assignment  Covered sections 5-1 and 5-2  Problems for hand in L20 HW (on webpage)  Problems for practice none  Reading for next class: sections 5-4 9/15/09 - L20 Flip FlopsCopyright 2009 - Joanne DeGroat, ECE, OSU15