1. Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003 Chapter 2: Clocked Storage Elements Operation

2. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic2 Evolution of a Latch : (a) keeper; information is latched (b) S-R latch; information can be modified (c) S-o-P latch; S-R latch that can implement a function – IMPORTANT !

3. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic3 Latching can be done only when clock is active, otherwise no change is allowed: (a) Clocked D-latch; (b) timing diagram of clocked D-latch Adding Clock Control to a Latch

4. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic4 (a) Basic Earl’s Latch; (b) Implementing the Carry function Importance of Latch S-o-P Configuration

5. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic5 (a) non-overlapping clocks; (b) single external clock; (c) timing diagram; (d) PowerPC 603 MS Latch (Gerosa, JSSC 12/94), Copyright © 1994 IEEE Master-Slave Latch

6. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic6 IBM LSSD Compatible Clocked Storage Element

7. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic7 True-single-phase-clock (TSPC) M-S latch Yuan and Svenson (1989), Copyright © 1989 IEEE

8. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic8 TSPC M-S Latch Operation

9. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic9 (a) local clock generator; (b) single latch; (c) clock signals Pulse latch (Kozu at al. 1996) Copyright © 1996 IEEE

10. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic10 Pulse latch: Intel’s explicit pulsed latch (Tschanz at al. 2001), Copyright © 2001 IEEE

11. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic11 (a) Early version of a flip-flop; (b) PDP-8 direct set-reset sequential element Flip-flop

12. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic12 (a) General flip-flop structure; (b) general M-S latch structure (a)(b) Difference between Flip-flop and M-S Latch

13. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic13 Experiment causing the flip-flop to fail while the M-S latch is still operational Data Q FF Clock F-F Data Q L Clock Data Latch Q L Q FF Flip-Flop failed ! Black-box view of the Flip-flop and M-S latch

14. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic14 Texas Instruments SN7474 Flip-flop Very much used and analyzed

15. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic15 Pulse generator block of SN7474: malfunctioning due to a gate-delay

16. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic16 Systematic Derivation of a FF using Karnaugh map Derivation of the pulse-generating stage of a flip-flop (only the Sn signal is shown)

17. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic17 (a) Pulse generator stage of the sense-amplifier flip-flop. (Madden and Bowhill, 1990); (b) Improvement for floating nodes. (Dobberpuhl, 1997); (c) Pulse generator stage improvement by proper design. (Nikolic and Oklobdzija, 1999). (a) (b) (c)

18. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic18 Creating the time reference points for opening and shutting the flip-flop

19. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic19 Hybrid-Latch Flip-Flop (HLFF) introduced by Partovi at al.

20. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic20 Logic representation of Partovi’s flip-flop (HLFF)

21. Nov. 15, 2003Digital System Clocking, Oklobdzija, Stojanovic, Markovic, Nedovic21 Systematically derived single-ended flip-flop (according to the slide no. 18) (a) (b) (a) circuit diagram; (b) logic representation. (Nedovic and Oklobdzija, 2000). Copyright © 2000 IEEE