1. Sequential MOS Logic Circuits
A. Marzuki

2. Introduction Sequential Circuit Behavior of Bistable Elements
SR Latch Circuit
Clocked Latch and Flip Flop Circuits
CMOS D-Latch and Edge-Triggered Flip-Flop

3. Classification of logic circuits based on temporal behaviour

4. Sequential circuit

5. BiStable simple analogy the energy function
Voltage gain of
inverters is larger
than unity at unstable Point,
a small voltage perturbation
at the input of any of the
inverters will be amplified,
causing the operation point
to move
to one of the stable points.
simple analogy the energy function
P ( x ) could be the potential energy of some one-dimensional
mechanical system. The gradient of P ( x ) is a “force”

6. Bistable At V01 = V02 Unstable condition
where gm  = (gmN  + gmP ) : All four
Transistor are in saturation
Direction
is determined
by initial
perturbation
polarity.
Output Expectation
(exponential!!!)

7. Continue… Gate Capacitance >>> Drain Capacitance Gate Charges
Derivative of small-signal gate voltages

8. Continue…
Combination above three equations

9. Continue…
Combination of two equation yields 2nd order differential equation
Time behaviour of gate charge q1

10. Continue…

11. Continue…

12. Continue…
Assume ~ Large t

13. SR Latch Circuit

14. Gate-level Schematic/Block Diagram.

15. Truth Table

16. Operation Mode

17. Capacitance

18. Circuit with Capacitance

19. Rise Time

20. Depletion Load nMOS (NOR2)

21. CMOS SR Latch circuit (NAND2)

22. Gate Schematic(NAND)

23. Truth Table

24. Depletion Load nMOS (NAND)

25. Clocked Latch and Flip-Flop Circuits

26. Sample Input-Output Waveforms

27. AOI Implementation (NOR)

28. Gate Schematic (NAND), active low

29. Gate Schematic (NAND), active high

30. Partial Block Diagram

31. Gate Schematic

32. Block Diagram

33. All NAND Implementation

34. Detailed Truth Table
J, K Compliments Q will go to J value at the next clock edge. J, K HIGH, the output will reverse its state after each clock pulse.

35. NOR-based JK Latch

36. AOI Realization(NOR)

37. Toggle Switch

38. Master-Slave Flip Flop

39. Master-Slave Flip Flop

40. Master-Slave Flip Flop (NOR)
CLK is HIGH MASTER is enable. Slave is disable and retains its previous state.
CLK is LOW is disconnected while input of slaves are simultaneously coupled to the output of the slaves.

41. CMOS D-Latch and Edge-Triggered Flip Flop

42. CMOS Implementation

43. Simplified Schematic View

44. Timing Diagram

45. 2nd CMOS Implementation

46. CMOS –ve Edge-triggered

47. Simulated Input-Output

48. Timing Violation

49. Layout

50. CMOS +ve Edge-triggered

51. Timing Diagram

52. References
Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test, JENS U. HORSTMANN, JSSC, FEB 1989.
S-M. Kang and Y. Leblebici ,CMOS Digital Integrated Circuits: Analysis and Design,, 3rd edition