1. Designing Sequential Logic Circuits
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

2. Sequential Logic Inputs Outputs Combinational Logic State
Clock
Next State
Current State
Inputs
Outputs
2 storage mechanisms:
• positive feedback
• charge-based

3. Naming Conventions In the text: Many different naming conventions:
a latch is level sensitive
a register is edge-triggered
Many different naming conventions:
flip-flops (level or edge?)
Transparency?
Dual edge/level

4. Latch versus Register
Latch- stores if clock is low transparent if clock is high
Register- stores if clock rises, never transparent (mostly) D Q D Q
Clk
Clk
Clk
Clk D D Q Q

5. Latch-Based Design N latch is transparent when f = 0
P latch is transparent when f = 1 f N P
Logic
Latch
Latch
Logic

6. Timing Definitions CLK t Register t t D Q D DATA CLK STABLE t t Q DATA
setup
hold D
DATA
CLK
STABLE t t c
lk2q Q
DATA
STABLE t

7. Maximum Clock Frequency
Timing Constraints:
tclk2q + tp(comb) + tsetup = T
tcdreg + tcdlogic > thold
First Constraint ensures clock is slow enough that Registers sample correct value
Second Constraint ensures that there is no path after the clock changes to alter the previously stored data
Register
LOGIC t
P(comb)

8. Positive Feedback: Bi-Stability1 A C B o 2 = o1
Vi2 1 o 1 o V V 5 2 i V
A,B Stable points
C is unstable:(metastable)
Feedback moves state to
Stable points, eventually 1 o V 5 i 2 V i 2 V o o V V i 1 2 = 1 = V o V V i 1 2

9. Writing a Static Latch
Use the clock to distinguish between the transparent and opaque states D
CLK
Forcing the state
(can implement as NMOS-only)
Converting into a MUX

10. Mux-Based Latches Negative latch Positive latch
(transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)
CLK 1 D Q 1 D Q
CLK

11. Master-Slave Register
CLK D Qm Q Qm D Q
CLK
CLK
Two opposite latches trigger on edge
Also called master-slave latch pair

12. Clk-Q Delay Clock to Q delays are D Different for rising and falling
Tclk-q
Clock to Q delays are
Different for rising and falling
Transitions
Use Worst Case – not Avg!

13. Setup Time (MS register)Q Qm D Q D Qm
CLK
Setup = 0.21nS
Passed D
Setup = 0.20nS
Failed to pass D

14. Cross-Coupled Pairs
NOR-based set-reset S 1 R 1 Q 1 - Q’ 1 - S Q R Q’

15. Cross-Coupled NAND Added clock Cross-coupled NANDs
This is not used in datapaths any more, but is a basic register memory cell

16. Output voltage dependence on transistor width
Sizing Issues 2
W=0.5
Q’ (V) 1
W=0.7
W=0.8
2.5
3.0
3.5 1 2
W=1
W/L (M5,M6) M2=6
Output voltage dependence on transistor width
Transient response

17. Storage Mechanisms
Static
Dynamic (charge-based)
CLK D Q
CLK

18. Making a Dynamic Latch Pseudo-Static

19. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

20. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

21. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

22. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

23. Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)

24. Setup/Hold Time Illustrations
Hold-1 case

25. Setup/Hold Time Illustrations
Hold-1 case

26. Setup/Hold Time Illustrations
Hold-1 case

27. Setup/Hold Time Illustrations
Hold-1 case

28. Setup/Hold Time Illustrations
Hold-1 case

29. Other Latches/Registers: C2MOS
“Keepers” can be added to make circuit pseudo-static

30. Insensitive to Clock-OverlapDD DD DD DD M M M M 2 6 2 6 M M 4 8 X X D Q D Q 1 M 1 M 3 7 M M M M 1 5 1 5
(a) (0-0) overlap
(b) (1-1) overlap

31. Pipelining
Reference
Pipelined

32. Other Latches/Registers: TSPC
Negative latch
(transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)

33. Pulse-Triggered Latches An Alternative Approach
Ways to design an edge-triggered sequential cell:
Master-Slave Latches
Pulse-Triggered Latch L1 L2 L
Data
Data D Q D Q D Q
Clk
Clk
Clk
Clk
Clk

34. Latch-Based Pipeline
~CLK
CLK
CLK F G F G

35. Non-Bistable Sequential Circuits─ Schmitt Trigger
VTC with hysteresis
Restores signal slopes

36. Noise Suppression: Schmitt Trigger

37. CMOS Schmitt Trigger
Moves switching threshold
of the first inverter

38. Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0 V
1.5 M 1
1.5
(V)
(V) X x
1.0 V
1.0 V M 2 V k
= 1 k
= 3 k
= 2
0.5
0.5 k
= 4
0.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5 V
(V) V
(V) in in
Voltage-transfer characteristics with hysteresis.
The effect of varying the ratio of the
PMOS device M
. The width is k
* m. m 4

39. CMOS Schmitt Trigger (2)

40. Multivibrator Circuits

41. Transition-Triggered Monostable

42. Monostable Trigger (RC-based)

43. Astable Multivibrators (Oscillators)1 2
N-1
Ring Oscillator
simulated response of 5-stage oscillator

44. Relaxation Oscillator

45. Voltage Controller Oscillator (VCO)

46. Differential Delay Element and VCO
ctrl o 2 1 in
delay cell v 1 2 3 4 in 2
two stage VCO
0.5
0.0
1.0
1.5
2.0
2.5
3.0 2 V 1 3 4
time (ns)
3.5
simulated waveforms of 2-stage VCO

47. Homework 7
A common way to characterize registers is to measure the timing aperture which is the total window in which transitions on data are not correctly output. This is done by making two clocks which are close, but not the same so that the relative phase drifts slowly with each cycle. Construct a pseudo-static master/slave flip-flop in SUE with the assumption that the input is driven by a unit inverter (2/1, min width nmos), the clock is driven by a 2x inverter. Optimize your designs to minimize the timing aperture (setup+hold) and clock to Q assuming the output load is 2 min inverters. Simulate your designs in SPICE and turn in both the designs (annotated schematics and spice results – plz. don’t waste paper!)
Do problem 1 again, with TSPC based flipflop. (High performance)