1. Digital Logic Design ESGD2201
University of Palestine
Faculty of Engineering and Urban planning
Software Engineering Department
Digital Logic Design ESGD2201
Lecture 16
Flip Flops and Related Devices
Eng. Mohammed Timraz
Electronics & Communication Engineer
Saturday, 26th December 2009

2. Flip Flops and Related Devices
Agenda
Flip Flops and Related Devices
Latches.
Edge-Triggered Flip-Flops.
Flip-Flop Operating Characteristics.
Flip-Flop Applications.
One-Shots.
The 555 Timer.

3. Flip Flops and Related Devices.
INTRODUCTION:
This chapter begin a study of the fundamentals of sequential logic. Bistable, monostable, and astable logic devices called multivibrators are covered.
Two categories of bistable devices are the latch and the flip-flop. Bistable devices have two stable states, called SET and RESET; they can retain either of these states indefinitely, making them useful as storage devices.
The basic difference between latches and flip-flops is the way in which they are changed from one state to the other.

4. Flip Flops and Related Devices.
INTRODUCTION:
The flip-flop is a basic building block for counters, registers, and other sequential control logic and is used in certain types of memories.
The monostable multivibrator, commonly known as the one-shot, has only one stable state.
A one-shot produces a single controlled-width pulse when activated or triggered.
The astable multivibrator has no stable state and is used primarily as an oscillator, which is a self-sustained waveform generator.
Pulse oscillators are used as the sources for timing waveforms in digital systems.

5. Flip Flops and Related Devices.
INTRODUCTION:
The focus in this chapter is the timing circuit portion of the system that produces the clock,
For example, the long time interval for the red and green lights, and the short time interval for the caution light.
The clock is used as the basic system timing signal for advancing the sequential logic through its states.

6. Flip Flops and Related Devices.
1. LATCHES:
The latch is a type of temporary storage device that has two stable states (bistable) and is normally placed in a category separate from that of flip-flops.
Latches are similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs.
The main difference between latches and flip-flops is in the method used for changing their state.

7. Flip Flops and Related Devices.
1. LATCHES:
Latches in Computers:
Latches are sometimes used in computer systems for multiplexing data onto a bus.
For example, data being input to a computer from an external source have to share the data bus with data from other sources.
When the data bus becomes unavailable to the external source, the existing data must be temporarily stored, and latches placed between the external source and the data bus may be used to do this.
When the data bus is unavailable to the external source, the latches must be disconnected from the bus using a method known as tristating.
When the data bus becomes available, the external data pass through the latches, thus the term transparent latch.
The gated D latch performs this function because when it is enabled, the data on its input appear on the output just as though there were a direct connection.
Data on the input are stored as soon as the latch is disabled.

8. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
FIGURE 1, S-R Latch as Logic gates

9. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
To explain the operation of the latch, we will use the NAND gate S-R latch in Figure 1 (b).
This latch is redrawn in Figure 2. with the negative - OR equivalent symbols used for the NAND gates.
FIGURE 2, Negative-OR equivalent of the NAND gate S-R latch

10. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
This is done because LOW on
the S and R lines are the activating inputs.
The latch in Figure 2 has two inputs,
S and R, and two outputs, Q and .
Let's start by assuming that both inputs and the Q output are HIGH. Since the Q output is connected
back to an input of gate G2, and the input is HIGH, the output of G2 must be LOW.
This LOW output is coupled back to an input of gate G1. Ensuring that its output is HIGH.
FIGURE 2.

11. 1.1 The S-R (SET-RESET) Latch:
The three modes of basic S-R latch operation
(SET, RESET, no-change) and the invalid condition.
When the Q output is HIGH, the latch is in the SET state.
It will remain in this state indefinitely until LOW is temporarily applied to the input.
With a LOW on the input and a HIGH on , the output of gate G2 is forced HIGH. This HIGH on the output is coupled back to an input of G1 , and since the S input is HIGH, the output of G1 goes LOW.
FIGURE 3,

12. 1.1 The S-R (SET-RESET) Latch:
The three modes of basic S-R latch operation
(SET, RESET, no-change) and the invalid condition.
FIGURE 3,

13. 1.1 The S-R (SET-RESET) Latch:
The three modes of basic S-R latch operation
(SET, RESET, no-change) and the invalid condition.
FIGURE 3,

14. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
Truth table for an active-LOW input S-R latch.

15. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
Logic symbols for both the active-HIGH input
and the active-LOW input latches are shown in Figure 4.
FIGURE 4.

16. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
Example 1:
illustrates how an active-LOW input S-R latch responds to conditions on
its inputs.
LOW levels are pulsed on each input in a certain sequence and the resulting Q output waveform is observed.
The = 0, = 0 condition is avoided because it results in
an invalid mode of operation and is a major drawback of any SET-RESET type of latch

17. Flip Flops and Related Devices.
1. LATCHES:
1.1 The S-R (SET-RESET) Latch:
Solution:
If the and waveforms in Figure 5 (a) are applied
to the inputs of the latch in Figure 4 (b), determine the
waveform that will be observed on the Q output.
Assume that Q is initially LOW.
FIGURE 5.