1. Flip-Flops and Related Devices
第八章
正反器及其相關元件
Flip-Flops and Related Devices
Latches 栓鎖電路
Edge-Triggered Flip-Flops 邊緣觸發正反器
Master-Slave Flip-Flops 主從式正反器
Flip-Flop Operating Characteristics 正反器運作特性
Flip-Flop Applications 正反器的用途
One-Shots 單擊(單觸發)
The 555 Timer (555定時器)
Troubleshooting 檢修
Programmable Logic 可程式邏輯
Digital System Application 數位系統的應用

2. 8-1 Latches 栓鎖電路 Active High, Active Low S-R Latch Contact Bounce
Gated S-R Latch
Gated D Latch

3. Latches 栓鎖電路
Figure Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

4. Latches 栓鎖電路
Figure Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

5. Latches 栓鎖電路 原來Q是1, 脈波來之後Q不變 原來Q是0, 脈波來之後Q變成1 原來Q是1, 脈波來之後Q變成0
當輸入端同時由0變成1時, 輸出的值不確定
當輸入端都是1時, 輸出不變
Figure The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition.

6. Figure 8--4 Logic symbols for the S-R and S-R latch.
Latches 栓鎖電路
Figure Logic symbols for the S-R and S-R latch.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

7. 例題8-1 若將圖8-5(a)的波形加到圖8-4(b)的輸入端, 試繪出其輸出波形, 假設輸出端Q的起始值為0.
Latches 栓鎖電路
例題8-1 若將圖8-5(a)的波形加到圖8-4(b)的輸入端, 試繪出其輸出波形, 假設輸出端Q的起始值為0.
Figure 8--5
Thomas L. Floyd Digital Fundamentals, 8e
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8. Figure 8--6 The S-R latch used to eliminate switch contact bounce.
Latches 栓鎖電路
Figure The S-R latch used to eliminate switch contact bounce.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

9. Figure A--13 The 74LS279 quad S-R latch.
Latches 栓鎖電路
Figure A The 74LS279 quad S-R latch.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

10. Figure 8--7 A gated S-R latch.
Latches 栓鎖電路
Figure A gated S-R latch.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

11. 例題8-2 若將圖8-9(a)的波形加到圖8-8的輸入端, 試繪出其輸出波形, 假設該Gated S-R Latch的起始狀態為RESET.
Latches 栓鎖電路
例題8-2 若將圖8-9(a)的波形加到圖8-8的輸入端, 試繪出其輸出波形, 假設該Gated S-R Latch的起始狀態為RESET.
Figure 8--8
Thomas L. Floyd Digital Fundamentals, 8e
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12. Figure 8--9 A gated D latch.
Latches 栓鎖電路
Figure A gated D latch.
Thomas L. Floyd Digital Fundamentals, 8e
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13. 例題8-3 若將圖8-11(a)的波形加到圖8-10的輸入端, 試繪出其輸出波形, 假設該Gated D Latch的起始狀態為RESET.
Latches 栓鎖電路
例題8-3 若將圖8-11(a)的波形加到圖8-10的輸入端, 試繪出其輸出波形, 假設該Gated D Latch的起始狀態為RESET.
Figure 8--10
Thomas L. Floyd Digital Fundamentals, 8e
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14. Figure A--14 The 74LS75 quad gated D latches.
Thomas L. Floyd Digital Fundamentals, 8e
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15. 表示邊緣觸發 正緣 觸發 負緣 觸發 加圓 圈 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).
Thomas L. Floyd Digital Fundamentals, 8e
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16. 8-2 Edge-Triggered Flip-Flops 邊緣觸發正反器
正緣觸發, 負緣觸發
邊緣觸發脈波產生器
邊緣觸發S-R正反器
邊緣觸發D型正反器
邊緣觸發J-K正反器
具有非同步的Preset及Clear端之J-K正反器

17. Figure 8--12 Operation of a positive edge-triggered S-R flip-flop.
2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Operation of a positive edge-triggered S-R flip-flop.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

18. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
例題8-4 若將圖8-16(a)的波形加到圖8-15的輸入端, 試繪出其輸出波形Q及Q, 假設該正緣觸發的S-R正反器之起始狀態為RESET.
Figure 8--13
Figure 8--14
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19. Figure 8--15 Edge triggering.
2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Edge triggering.
Thomas L. Floyd Digital Fundamentals, 8e
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20. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.
Thomas L. Floyd Digital Fundamentals, 8e
2. Edge-Triggered Flip-Flops 邊緣觸發正反器
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21. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.
Thomas L. Floyd Digital Fundamentals, 8e
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22. D Flip-Flop = S-R Flip-Flop + Invertor
2. Edge-Triggered Flip-Flops 邊緣觸發正反器
D Flip-Flop = S-R Flip-Flop + Invertor
Figure A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

23. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
例題8-5 若將圖8-21(a)的波形加到一個正緣觸發的DFF之輸入端, 試繪出其輸出波形Q, 假設該正緣觸發的D型正反器之起始狀態為RESET.
Figure 8--19
Thomas L. Floyd Digital Fundamentals, 8e
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24. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure A simplified logic diagram for a positive edge-triggered J-K flip-flop.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

25. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Transitions illustrating the toggle operation when J =1 and K = 1.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

26. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
例題8-6 若將圖8-24(a)的波形加到一個負緣觸發的JKFF之輸入端, 試繪出其輸出波形Q, 假設該負緣觸發的JK型正反器之起始狀態為RESET.
Figure 8--22
Thomas L. Floyd Digital Fundamentals, 8e
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27. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
例題8-7 若將圖8-25(a)的波形加到一個正緣觸發的JKFF之輸入端, 試繪出其輸出波形Q, 假設該正緣觸發的JK型正反器之起始狀態為RESET.
Figure 8--23
Thomas L. Floyd Digital Fundamentals, 8e
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28. 非同步的Preset及Clear端 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

29. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

30. Figure 8--26 Open file F08-28 to verify the operation.
2. Edge-Triggered Flip-Flops 邊緣觸發正反器
例題8-8 若將圖8-28(a)的波形加到一個具有Preset及Clear端的正緣觸發的JKFF之輸入端, 試繪出其輸出波形Q, 假設該正緣觸發的JK型正反器之起始狀態為RESET.
Figure Open file F08-28 to verify the operation.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

31. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure A Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops.

32. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
Figure A Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

33. 2. Edge-Triggered Flip-Flops 邊緣觸發正反器
例題8-9 若將圖8-31(a)的波形加到74HC112的其中一個負緣觸發的JKFF之輸入端, 試繪出其輸出波形Q, 假設該負緣觸發的JK型正反器之起始狀態為RESET.
Figure 8--27
Thomas L. Floyd Digital Fundamentals, 8e
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34. Figure 8--28 Basic logic diagram for a master-slave J-K flip-flop.
8-3 Master-Slave Flip-Flops 主從式正反器
3. Master-Slave Flip-Flops 主從式正反器
Figure Basic logic diagram for a master-slave J-K flip-flop.
Thomas L. Floyd Digital Fundamentals, 8e
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

35. 3. Master-Slave Flip-Flops 主從式正反器
資料在Clock正緣來的時候被載入, 而在Clock負緣來的時候輸出
資料在Clock負緣來的時候被載入, 而在Clock正緣來的時候輸出
Figure Pulse-triggered (master-slave) J-K flip-flop logic symbols.

36. 3. Master-Slave Flip-Flops 主從式正反器
例題8-10 若將圖8-34(a)的波形加到一個主從式的JKFF之輸入端, 試繪出其輸出波形Q, 假設該主從式的JK型正反器之起始狀態為RESET.
Figure 8--30
Thomas L. Floyd Digital Fundamentals, 8e
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37. 8-4. 正反器的運作特性 Flip-Flop Operating Characteristics
Propagation Delay Times 極際延遲時間
Set-up Time 建立的時間
Hold Time 維持的時間
Maximum Clock Frequency 最高鐘脈波頻率
Pulse Width 脈波寬度
Power Dissipation 功率消耗

38. Figure 8--31 Propagation delays, clock to output.
4.Flip-Flop Operating Characteristics 正反器運作特性
Figure Propagation delays, clock to output.
Thomas L. Floyd Digital Fundamentals, 8e
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39. 4.Flip-Flop Operating Characteristics 正反器運作特性
Figure Propagation delays, preset input to output and clear input to output.
Thomas L. Floyd Digital Fundamentals, 8e
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40. 4.Flip-Flop Operating Characteristics 正反器運作特性
Figure Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.
Thomas L. Floyd Digital Fundamentals, 8e
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41. 4.Flip-Flop Operating Characteristics 正反器運作特性
Figure Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry.
Thomas L. Floyd Digital Fundamentals, 8e
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42. 8-5 Flip-Flop Applications 正反器的用途
並聯資料暫存器
除法器
除4 電路, 除8 電路
用正反器來產生二進制的計數順序

43. 並聯資料暫存器 5. Flip-Flop Applications 正反器的用途
Figure Example of flip-flops used in a basic register for parallel data storage.
Thomas L. Floyd Digital Fundamentals, 8e
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44. 除法器 5. Flip-Flop Applications 正反器的用途
Figure The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.
Thomas L. Floyd Digital Fundamentals, 8e
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45. 除4 電路 5. Flip-Flop Applications 正反器的用途
Figure Example of two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.
Thomas L. Floyd Digital Fundamentals, 8e
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46. 5. Flip-Flop Applications 正反器的用途
例題8-11試繪出圖8-42 fout 的輸出波形,若將一個8KHz的方波加到圖8-42的 fin , 假設該正緣觸發的JK型正反器之起始狀態為RESET.
除8 電路
Figure 8--38
Figure 8--39
Thomas L. Floyd Digital Fundamentals, 8e
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47. 用正反器來產生二進制的計數順序 5. Flip-Flop Applications 正反器的用途
Figure Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.
Thomas L. Floyd Digital Fundamentals, 8e
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48. 例題8-12 試繪出圖8-45 中的CLK 與 QA,QB,QC 的波形關係, 並用二進制表示該組輸出波型 .
5. Flip-Flop Applications 正反器的用途
例題8-12 試繪出圖8-45 中的CLK 與 QA,QB,QC 的波形關係, 並用二進制表示該組輸出波型 .
Figure 8--41
Figure 8--42
Thomas L. Floyd Digital Fundamentals, 8e
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49. 8-6 One-Shots 單擊器(單觸發) 簡單的單擊器 Mono-stable Multivibrator 單穩態多諧震盪器
Non-retriggerable one-shot 不可再觸發的單擊器
Retriggerable one-shot不可再觸發的單擊器

50. Figure 8--43 A simple one-shot circuit.
6. One-Shots 單擊(單觸發)
Figure A simple one-shot circuit.
Thomas L. Floyd Digital Fundamentals, 8e
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51. 6. One-Shots 單擊(單觸發)
Figure Basic one-shot logic symbols. CX and RX stand for external components.
Thomas L. Floyd Digital Fundamentals, 8e
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52. Figure 8--45 Nonretriggerable one-shot action.
6. One-Shots 單擊(單觸發)
這些脈波將被忽略
Figure Nonretriggerable one-shot action.
Thomas L. Floyd Digital Fundamentals, 8e
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53. Figure 8--46 Retriggerable one-shot action.
6. One-Shots 單擊(單觸發)
重新計時
Figure Retriggerable one-shot action.
Thomas L. Floyd Digital Fundamentals, 8e
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54. Figure 8--47 A sequential timing circuit using three one-shots.
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55. 8-7 The 555 Timer (555定時器) 555的內部方塊圖 用555作成單擊器 用555作成不穩態多諧震盪器
改善555的 Duty Cycle

56. 7. The 555 Timer (555定時器)
Figure Internal functional diagram of a 555 timer (pin numbers are in parenthesis).
Thomas L. Floyd Digital Fundamentals, 8e
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57. Figure 8--49 The 555 timer connected as a one-shot.
Thomas L. Floyd Digital Fundamentals, 8e
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58. Figure 8--50 One-shot operation of the 555 timer.
觸發後電容器開始充電 平常
電容器充到超過Thresh電壓, 正反器被Reset, 電晶體導通, 電容器急速放電
Figure One-shot operation of the 555 timer.
Thomas L. Floyd Digital Fundamentals, 8e
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59. 不穩態多諧震盪器 7. The 555 Timer (555定時器)
Figure The 555 timer connected as an astable multivibrator (oscillator).
Thomas L. Floyd Digital Fundamentals, 8e
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60. Figure 8--52 Operation of the 555 timer in the astable mode.
Thomas L. Floyd Digital Fundamentals, 8e
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61. 7. The 555 Timer (555定時器)
Figure Frequency of oscillation as a function of C1 and R1 1 2R2. The sloped lines are values of R1 1 2R2.
Thomas L. Floyd Digital Fundamentals, 8e
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62. 由於充電時, 電流經過R1及R2, 但放電時, 電流只經過R2, 因此輸出波形並不對稱, 可加Diode改進.
7. The 555 Timer (555定時器)
由於充電時, 電流經過R1及R2, 但放電時, 電流只經過R2, 因此輸出波形並不對稱, 可加Diode改進.
Figure The addition of diode D1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R1 , R2.
Thomas L. Floyd Digital Fundamentals, 8e
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63. 例題8-16 如圖8-55所示為一個555的不穩態多諧震盪器, 試算出其輸出頻率及Duty Cycle.
7. The 555 Timer (555定時器)
例題8-16 如圖8-55所示為一個555的不穩態多諧震盪器, 試算出其輸出頻率及Duty Cycle.
Sol:
f = 1.44/(R1+2R2)C1
= 5.64KHz
Duty Cycle =
((R1+R2)/(R1+2R2))100%
= 59.5%
Figure 8--63
Thomas L. Floyd Digital Fundamentals, 8e
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64. Figure A--18 Three ways to set the pulse width of a 74121.不可再觸發的單擊器
6. One-Shots 單擊(單觸發)
tw = 0.7REXTCEXT
tw = 30ns
tw = 0.7(2kΩ)CEXT
Figure A Three ways to set the pulse width of a 不可再觸發的單擊器
Thomas L. Floyd Digital Fundamentals, 8e
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65. 6. One-Shots 單擊(單觸發)
Figure A Logic symbol for the 74LS122 retriggerable one-shot.可再觸發的單擊器
Thomas L. Floyd Digital Fundamentals, 8e
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66. 例題A-1 在某些應用裡, 我們需要一個脈波寬度大約100ms的單擊器, 試用一個74121來設計, 並列出各零件的數值.
6. One-Shots 單擊(單觸發)
例題A-1 在某些應用裡, 我們需要一個脈波寬度大約100ms的單擊器, 試用一個74121來設計, 並列出各零件的數值.
SOL:
Figure A--19
若電容一定要用
3.3 μF,
tw = 0.7REXTCEXT,
REXT= tw / 0.7 CEXT
= 43.29KΩ
因此可選用一個39KΩ的電阻再串接一個5KΩ的可變電阻來微調.
隨意選用一個39KΩ的電阻, tw = 0.7REXTCEXT,
CEXT = tw / 0.7REXT
= 100x10-3S/0.7(39K Ω)
= 3.66x10-6F
= 3.66 μF
Thomas L. Floyd Digital Fundamentals, 8e
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67. 8-8 Troubleshooting 檢修
Figure Two-phase clock generator with ideal waveforms. Open file F08-64 and verify the operation.雙相位鐘脈波產生器
Thomas L. Floyd Digital Fundamentals, 8e
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68. Figure 8--57 Logic analyzer displays for the circuit in Figure 8-64.
8. Troubleshooting 檢修
Figure Logic analyzer displays for the circuit in Figure 8-64.
Thomas L. Floyd Digital Fundamentals, 8e
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69. 改用負緣觸發的正反器可改善Glitch現象
8. Troubleshooting 檢修
改用負緣觸發的正反器可改善Glitch現象
Figure Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F08-66 and verify the operation.
Thomas L. Floyd Digital Fundamentals, 8e
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