Presentation is loading. Please wait.

Presentation is loading. Please wait.

Delay/Phase Regeneration Circuits Crescenzo D’Alessandro, Andrey Mokhov, Alex Bystrov, Alex Yakovlev Microelectronics Systems Design Group School of EECE.

Published byKent Pilley Modified over 9 years ago

Similar presentations

Presentation on theme: "Delay/Phase Regeneration Circuits Crescenzo D’Alessandro, Andrey Mokhov, Alex Bystrov, Alex Yakovlev Microelectronics Systems Design Group School of EECE."— Presentation transcript:

1 Delay/Phase Regeneration Circuits Crescenzo D’Alessandro, Andrey Mokhov, Alex Bystrov, Alex Yakovlev Microelectronics Systems Design Group School of EECE Newcastle University, UK

2 ASYNC 2007 - C D'Alessandro et al. - 2/28 Outline Introduction Background on Phase-encoding Dual-rail/multiple-rail phase encoding Motivation for the present work Taxonomy Latch-based designs MUTEX-based designs Design types Conclusions

3 ASYNC 2007 - C D'Alessandro et al. - 3/28 Phase Encoding Dual-Rail Main idea: encode data on the phase relationship between two identical out- of-phase signals Resistant to transient faults Similarity with dual-rail dual-spacer protocol

4 ASYNC 2007 - C D'Alessandro et al. - 4/28 Multiple Rail No group of wires has the same delay All wires toggle when an item of data is sent

5 ASYNC 2007 - C D'Alessandro et al. - 5/28 Phase Corruption Phase corruption is due to jitter (introduced by the gates), physical wire fabric and transistor mismatches Mismatch in process variations cause a systematic delay offset to appear between the two lines, which could cause errors in decoding Additionally, cross-talk causes symbol-dependent phase corruption As the wires are always “allies” in terms of cross-talk, the longer the wire, the more corrupted the phase relationship between the wires What is then the optimal length of wire which “guarantees” that the phase relationship is maintained?

6 ASYNC 2007 - C D'Alessandro et al. - 6/28 Phase Corruption Example of phase corruption No change in sequence Change in absolute value of phase

7 ASYNC 2007 - C D'Alessandro et al. - 7/28 Taxonomy Different design styles can be identified We focus in this presentation on digital implementations Latch-based designs A latch is used on each wire Gate-level implementation Transistor-level implementation MUTEX-based designs A single MUTEX is used to arbitrate between the two edges “Early-propagating” “Merging”

8 ASYNC 2007 - C D'Alessandro et al. - 8/28 Parameters Maximum input time separation affected δ max Events whose time separation is > δ max retain their original separation Circuit latency λ Time between the first event occurring and the corresponding output being generated Response time ζ Time between the two events below which the time separation cannot be regenerated Capture range κ= δ max – ζ Using the convention sometimes used in PLLs to give a value for the range Linearity

9 ASYNC 2007 - C D'Alessandro et al. - 9/28 Graphs δ max λ ζ κ Linearity: how flat this part is

10 ASYNC 2007 - C D'Alessandro et al. - 10/28 Passive Solution “Textbook” solution Different response for rising/falling – can be matched using balanced drivers Not very linear Capacitor size a problem – also introduces latency

11 ASYNC 2007 - C D'Alessandro et al. - 11/28 Latch-based Gate level/1

12 ASYNC 2007 - C D'Alessandro et al. - 12/28 Latch-based Gate level/1 Latches are transparent at startup They are closed after one edge arrives at the output They are then reopened after the pulse is finished 6 FO4 capture range, stops working around 5 FO4 input delta Difference in rising and falling behaviour

13 ASYNC 2007 - C D'Alessandro et al. - 13/28 Latch-based Gate level/2 Similar to previous design Two pulse generators – faster Only blocks one output and not both Only one output used – less difference between rising and falling edges

14 ASYNC 2007 - C D'Alessandro et al. - 14/28 Latch-based Transistor level

15 ASYNC 2007 - C D'Alessandro et al. - 15/28 Latch-based T ransistor level Better latency and response Capture range can be increased increasing tau Good linearity

16 ASYNC 2007 - C D'Alessandro et al. - 16/28 MUTEX-based

17 ASYNC 2007 - C D'Alessandro et al. - 17/28 MUTEX-based Higher latency (complex gates) Good response and capture range Poor linearity Early-propagating

18 ASYNC 2007 - C D'Alessandro et al. - 18/28 MUTEX-based “Infinite” capture range – lower-bounded Flat response Very high latency – dependent on input time separation NOR-MUTEX is slow

19 ASYNC 2007 - C D'Alessandro et al. - 19/28 STG for Repeater STG for a repeater Use timing assumptions: i1- -> p1 -> g11-, g12- g11- -> i1+ … and mirror ones This STG can be synthesised using PETRIFY Synthesised version in next slide…

20 ASYNC 2007 - C D'Alessandro et al. - 20/28 MUTEX-based w/PETRIFY Very good linearity and capture range High latency independent on input until 0.5 FO4 Generated using PETRIFY (STG in previous slide)

21 ASYNC 2007 - C D'Alessandro et al. - 21/28 TSE Transition Sequence Encoder This circuit generates a number of requests based on an input matrix The acknowledgments can be either “proper” or a delayed version of the output signals Can be used as a phase-encoder

22 ASYNC 2007 - C D'Alessandro et al. - 22/28 MUTEX-TSE This solution is similar to the MUTEX-based one, only using the TSE as a sender λ < 2 FO4 Increasing output time separation dependent on the input (output δ > 8FO4)

23 ASYNC 2007 - C D'Alessandro et al. - 23/28 TSE – Transistor-level Like above, only rising and falling edge Transistor-level implementation of the TSE Results similar to the previous case Note the similarity with the transistor-level latch-based design

24 ASYNC 2007 - C D'Alessandro et al. - 24/28 Multiple-rail Multiple-rail phase-encoding requires similar designs to regenerate the phase relationship The design on the right is a simple expansion of the previous latch-based design Very slow response Only useful for large δ Acceptable latency

25 ASYNC 2007 - C D'Alessandro et al. - 25/28 Multiple-rail “merge” Better design: use a TSE Shown: 3-wires regeneration – left, rising edge only, right; rising and falling edges Better response, but λ depends on the input time separation (needs to wait for all inputs to be present)

26 ASYNC 2007 - C D'Alessandro et al. - 26/28 Performance comparison Dual-rail implementations Area in transistor count κ and λ in FO4 Area and energy for “Latch-based transistor level” design is for no keeper/keeper “Charge compensation”: area calculated estimating the size of the capacitors Avg. for rise/fall DesignAreapJ/bitζκλ Latch-based 1580.826 (avg)22.5 Latch-based 2680.59433.5 Mod. MUTEX881.17<0.517 Automatic Synthesis 940.9<0.157 MUTEX-based merging 1100.98<0.1  δ input Latch-based transistor level 28/320.43/0.47<0.53 11 Charge- compensation 240.22244 (avg) TSE gate-level740.78<0.1  δ input TSE transistor- level 520.79<0.1  δ input

27 ASYNC 2007 - C D'Alessandro et al. - 27/28 Conclusions Some phase-regeneration circuits have been presented More work to do: Metastability behaviour, in particular for keeper structures Behaviour in case of faults Characterisation with different input signal slopes

28 ASYNC 2007 - C D'Alessandro et al. - 28/28 Contact details Crescenzo S. D’Alessandro Microelectronics Systems Design Group School of Electrical, Electronics and Computer Engineering Merz Court Newcastle University, UK Crescenzo.D’Alessandro@ncl.ac.uk http://async.org.uk

Download ppt "Delay/Phase Regeneration Circuits Crescenzo D’Alessandro, Andrey Mokhov, Alex Bystrov, Alex Yakovlev Microelectronics Systems Design Group School of EECE."

Similar presentations

Topics Electrical properties of static combinational gates:

Topics Electrical properties of static combinational gates:
Self-Timed Logic Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical and.

Self-Timed Logic Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical and.
Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev Dual-Rail Control Logic for Enhanced Circuit Robustness.

Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev Dual-Rail Control Logic for Enhanced Circuit Robustness.
Data Synchronization Issues in GALS SoCs Rostislav (Reuven) Dobkin and Ran Ginosar Technion Christos P. Sotiriou FORTH ICS- FORTH.

Data Synchronization Issues in GALS SoCs Rostislav (Reuven) Dobkin and Ran Ginosar Technion Christos P. Sotiriou FORTH ICS- FORTH.
Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.

Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.
Chapter 13 Transmission Lines

Chapter 13 Transmission Lines
Self-Timed Systems Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical.

Self-Timed Systems Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical.
Storey: Electrical & Electronic Systems © Pearson Education Limited 2004 OHT 10.1 Sequential Logic  Introduction  Bistables  Memory Registers  Shift.

Storey: Electrical & Electronic Systems © Pearson Education Limited 2004 OHT 10.1 Sequential Logic  Introduction  Bistables  Memory Registers  Shift.
Digital Logic Chapter 5 Presented by Prof Tim Johnson

Digital Logic Chapter 5 Presented by Prof Tim Johnson
Digital Logic Design Lecture # 17 University of Tehran.

Digital Logic Design Lecture # 17 University of Tehran.
Digital Logic Circuits (Part 2) Computer Architecture Computer Architecture.

Digital Logic Circuits (Part 2) Computer Architecture Computer Architecture.
Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004.
Clock Design Adopted from David Harris of Harvey Mudd College.

Clock Design Adopted from David Harris of Harvey Mudd College.
RTL Hardware Design by P. Chu Chapter 161 Clock and Synchronization.

RTL Hardware Design by P. Chu Chapter 161 Clock and Synchronization.
© 2003-2009 Ran Ginosar048878 Lecture 3: Handshake Ckt Implementations 1 VLSI Architectures 048878 Lecture 3 S&F Ch. 5: Handshake Ckt Implementations.

© Ran Ginosar Lecture 3: Handshake Ckt Implementations 1 VLSI Architectures Lecture 3 S&F Ch. 5: Handshake Ckt Implementations.
Chapter 9 Memory Basics Henry Hexmoor1. 2 Memory Definitions  Memory ─ A collection of storage cells together with the necessary circuits to transfer.

Chapter 9 Memory Basics Henry Hexmoor1. 2 Memory Definitions  Memory ─ A collection of storage cells together with the necessary circuits to transfer.
1 Clockless Logic Montek Singh Tue, Mar 23, 2004.

1 Clockless Logic Montek Singh Tue, Mar 23, 2004.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 –Selected Design Topics Part 3 – Asynchronous.

Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 –Selected Design Topics Part 3 – Asynchronous.
Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.

Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.
ELEC 6200, Fall 07, Oct 24 Jiang: Async. Processor 1 Asynchronous Processor Design for ELEC 6200 by Wei Jiang.

ELEC 6200, Fall 07, Oct 24 Jiang: Async. Processor 1 Asynchronous Processor Design for ELEC 6200 by Wei Jiang.

Similar presentations

Ads by Google