1. 1 Sequential Systems A combinational system is a system whose outputs depend only upon its current inputs. A sequential system is a system whose outputs depends on the current inputs and the system’s current state. All systems we have looked at to date have been combinational systems.

2. 2 Flip-Flops/ Latches Latches and Flip-Flops are devices that can have two internal states (0,1) The output of a latch or a Flip-Flop (FF) is dependent upon its CURRENT STATE and CURRENT INPUTS. Latches and FF’s are the simplest examples of sequential systems.

3. 3 Set/ Reset Nor Latch (SR Nor Latch) S R Ps Ns L L Q Q L H X L H L X H H H X - Present State Next State SQ R Q’Q’ R S Q Q’Q’ Implementation Symbol inputs,outputs high true. S R Ps Ns 0 0 Q Q 0 1 X 0 1 0 X 1 1 1 X -

4. 4 Set/ Reset Nor Latch (SR Nor Latch) SQ R Q’Q’ Operation Example: S R Ps Ns 0 0 Q Q 0 1 X 0 1 0 X 1 1 1 X - Not Allowed

5. 5 SR latch Operation R=0 S=0  1 Q Q’ SET operation 1  0 0  1R=0  1 S=0 Q Q’ RESET operation 1  0 0  1 1  0

6. 6 SR latch Operation (cont) R=0 S=0 Q Q’ Stable when S=R=0, Q=1 0 0 1 1 R=0 S=0 Stable when S=R=0, Q’=1 1 1 0 0 Q Q’

7. 7 What about S=R=1? (Set,Reset both true?) R=0  1 Q Q’ 0 0 1  0 S=0  1 Assume that S, R both transition to 1 simultaneously. Q becomes ‘0’, but Q’ remains ‘0’! Outputs are no longer complements of each other.

8. 8 What happens when S,R return to 0? R=1  0 Q Q’ 0  1  0  1  0  1 S=1  0 0  1  0  1  0  1 Oscillation occurs if S,R return to 0 simultaneously! At some point the system will settle into a stable condition. The bottom line is that S=R=1 is an illegal input condition (or design the SR latch such that one input is DOMINANT).

9. 9 SR Latch, R dominant R Q’ S S R Ps Ns 0 0 Q Q 0 1 X 0 1 0 X 1 1 1 X 0 Q When S=R=1, then acts as a RESET (R is dominant)

10. 10 SR Nor Latch -- Characteristic Equation Not Allowed

11. 11 Terminology A bistable memory device is the generic term for the elements we are studying We can use the term latch or flip-flop to refer to these devices – latch: bistable memory device with level sensitive triggering (no clock) – flip-flop: bistable memory device with edge-triggering (with clock) Warning: Your author (Roth) uses the terminology Flip-Flop and Clocked Flip-Flop instead of latch and Flip-Flop – latch, flip-flop more standard

12. 12 Data Flip-Flop (D-FF, falling edge triggered) CK D Ps Ns 0 X Q Q 1 X Q Q 1  0 D X D Only time D-FF changes state is on a CLOCK EDGE. This D-FF is falling edge triggered. Changes state to whatever the D value was just before the clock neg. edge occurred. (Q+ = D) DQ CK Q’Q’ CK is the clock input. D input is only sampled at a clock edge.

13. 13 A Clock Waveform time voltage f = 1/  PwPw rising edgefalling edge  - period (in seconds) P w - pulse width (in seconds) f - frequency pulse width (in Hertz) duty cycle - ratio of pulse width to period (in %) duty cycle = P w / 

14. 14 D-FF Operation Example 1 D CK Q On falling edge of CK, D=1, so Q=1 On falling edge of C, D=0, so Q=0

15. 15 D-FF Operation Example 2

16. 16 Clocked T Flip-Flop (falling edge triggered) TQ CK Q’Q’ CK is the clock input. T input sampled only at a clock edge. Retain State Synchronous Toggle CK T Ps Ns 0 X Q Q 1 X Q Q 1  0 0 Q Q 1  0 1 Q Q ’ T-FF

17. 17 Clocked T-FF Operation Example T=1 Toggle T=0, Retain State T=1 Toggle

18. 18 Clocked JK Flip-Flop (falling edge triggered) CK J K Ps Ns 0 X X Q Q 1 X X Q Q 1  0 0 0 Q Q 1  0 0 1 X 0 1  0 1 0 X 1 1  0 1 1 Q Q ’ JQ CK Q’Q’ CK is the clock input. J,K inputs are sampled only at a clock edge. K Retain State Synchronous Reset Synchronous Set Synchronous Toggle

19. 19 Clocked JK-FF Operation Example J=1, K=0 Set J=0, K=1 Reset J=1, K=1 Toggle

20. 20 JK-FF Implementation DQ CK Q’Q’ Q K J This is a falling edge triggered JK-FF. We will derive this implementation at a later date.

21. 21 Master-Slave JK-FF Implementation S R Master Slave S R Q Q’Q’ P P’P’ J K

22. 22 J Q CK Q’Q’ K CLR PRE D Q CK Q’Q’ CLR Clocked FF’s with Asynchronous Preset and Clear Inputs The small inversion symbol on the preset and clear inputs indicate that these are active for a 0 state. These inputs are asynchronous, meaning that they override the clock and JK inputs (or clock and D inputs). CLR active  Q = 0 PRE active  Q=1

23. 23 Unclocked T-FF T FF S Q’Q’ Q R Q’Q’ Q Q’Q’ Q T

24. 24 Unclocked JK-FF Q’Q’ Q J FF S Q’Q’ Q R K Q’Q’ Q J K  J K Q

25. 25 D-FF Register Q’3Q’3 Q1 D3 CK CLR Q’2Q’2 Q1 D2 CK CLR Q’1Q’1 Q1 D1 CK CLR Q’0Q’0 Q0 D0 CK CLR 1 1 1 Clear Clock 0 ->1 0 ->0 0 ->1 0

26. 26 What do you have to know? Definition of a sequential system SR Nor latch, Clocked D-FF, T-FF, JK-FF (Master-Slave and Edge-Triggered) –Timing diagrams, state tables, characteristic eqns. Unclocked T-FF, JK-FF –Timing diagrams, state tables, characteristic eqns.