Presentation is loading. Please wait.

Presentation is loading. Please wait.

C H A P T E R 15 Memory Circuits

Published byCourtney Gateley Modified over 9 years ago

Similar presentations

Presentation on theme: "C H A P T E R 15 Memory Circuits"— Presentation transcript:

1 C H A P T E R 15 Memory Circuits
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

2 Figure 15.1 (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

3 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

4 Figure 15.3 (a) The set/reset (SR) flip-flop and (b) its truth table.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

5 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

6 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

7 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

8 Figure 15. 7 A simpler CMOS implementation of the clocked SR flip-flop
Figure 15.7 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

9 Figure 15.8 A block diagram representation of the D flip-flop.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

10 Figure 15. 9 A simple implementation of the D flip-flop
Figure 15.9 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase non-overlapping clock whose waveforms are shown in (b). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

11 Figure 15. 10 (a) A master–slave D flip-flop
Figure (a) A master–slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

12 Figure 15.11 A 2M+N -bit memory chip organized as an array of 2M rows × 2N columns.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

13 Figure 15.12 A CMOS SRAM memory cell.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

14 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

15 Figure The normalized value of VQ versus the ratio (W/L)5 /(W/L)1 for the circuit in Fig This graph can be used to determine the maximum value permitted for (W/L)5 /(W/L)1 so that is VQ kept below a desired level. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

16 Figure 15.15 Voltage waveforms at various nodes in the SRAM cell during a read-1 operation.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

17 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

18 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

19 Figure 15.18 The one-transistor dynamic RAM (DRAM) cell.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

20 Figure When the voltage of the selected word line is raised, the transistor conducts, thus connecting the storage capacitor CS to the bit-line capacitance CB. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

21 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

22 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

23 Figure An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

24 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

25 Figure 15.24 The active-loaded MOS differential amplifier as a sense amplifier.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

26 Figure 15. 25 A NOR address decoder in array form
Figure A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

27 Figure A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

28 Figure 15. 27 A tree column decoder
Figure A tree column decoder. Note that the colored path shows the transistors that are conducting when A0 = 1, A1 = 0, and A2 = 1, the address that results in connecting B5 to the data line. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

29 Figure (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/6tP. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

30 Figure 15. 29 (a) A one-shot or monostable circuit
Figure (a) A one-shot or monostable circuit. Utilizing a delay circuit with a delay T and an XOR gate, this circuit provides an output pulse of width T. (b) The delay circuit can be implemented as the cascade of N inverters where N is even, in which case T = NtP . Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

31 Figure 15.30 A simple MOS ROM organized as 8 words ×4 bits.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

32 Figure (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

33 Microelectronic Circuits, Sixth Edition
Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

34 Figure 15.33 The floating-gate transistor during programming.
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

35 Figure P15.11 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Download ppt "C H A P T E R 15 Memory Circuits"

Similar presentations

Fig. 13.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

Fig Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.
COEN 180 SRAM. High-speed Low capacity Expensive Large chip area. Continuous power use to maintain storage Technology used for making MM caches.

COEN 180 SRAM. High-speed Low capacity Expensive Large chip area. Continuous power use to maintain storage Technology used for making MM caches.
Transistors (MOSFETs)

Transistors (MOSFETs)
Operational Amplifiers 1. Copyright  2004 by Oxford University Press, Inc. Microelectronic Circuits - Fifth Edition Sedra/Smith2 Figure 2.1 Circuit symbol.

Operational Amplifiers 1. Copyright  2004 by Oxford University Press, Inc. Microelectronic Circuits - Fifth Edition Sedra/Smith2 Figure 2.1 Circuit symbol.
1. 2 3 4 5 6 Figure. 01 7 8 9 10 11 (a) 8 * 8 array (b) 16 * 8 array.

Figure (a) 8 * 8 array (b) 16 * 8 array.
Memory Section 7.2. Types of Memories Definitions – Write: store new information into memory – Read: transfer stored information out of memory Random-Access.

Memory Section 7.2. Types of Memories Definitions – Write: store new information into memory – Read: transfer stored information out of memory Random-Access.
Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.

Semiconductor Memory Design. Organization of Memory Systems Driven only from outside Data flow in and out A cell is accessed for reading by selecting.
CP208 Digital Electronics Class Lecture 11 May 13, 2009.

CP208 Digital Electronics Class Lecture 11 May 13, 2009.
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.
Memory Basics. 8-1 Memory definitions Memory is a collection of cells capable of storing binary information. Two types of memory: –Random-Access Memory.

Memory Basics. 8-1 Memory definitions Memory is a collection of cells capable of storing binary information. Two types of memory: –Random-Access Memory.
Operational Amplifiers

Operational Amplifiers
Introduction to CMOS VLSI Design Lecture 13: SRAM

Introduction to CMOS VLSI Design Lecture 13: SRAM
Data-Converter Circuits

Data-Converter Circuits
Topic 9 MOS Memory and Storage Circuits

Topic 9 MOS Memory and Storage Circuits
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 13 CMOS Digital Logic Circuits.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 13 CMOS Digital Logic Circuits.
1 The Basic Memory Element - The Flip-Flop Up until know we have looked upon memory elements as black boxes. The basic memory element is called the flip-flop.

1 The Basic Memory Element - The Flip-Flop Up until know we have looked upon memory elements as black boxes. The basic memory element is called the flip-flop.
Chapter 10. Memory, CPLDs, and FPGAs

Chapter 10. Memory, CPLDs, and FPGAs
11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.

11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.
Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES.

Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES.
Introduction to CMOS VLSI Design SRAM/DRAM

Introduction to CMOS VLSI Design SRAM/DRAM

Similar presentations

Ads by Google