1. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 The Front End Electronics for the HADES RPC wall (ESTRELA_FEE) Daniel Belver (University of Santiago de Compostela) Collaborators:

2. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 HADES (High Acceptance Di-Electron Spectrometer) HADES is an experiment devoted to study the nuclear matter properties through the di-electron decay of vector mesons produced in pp and NN collisions at kinetic energies from 1-2 GeV/A. HADES is an experiment devoted to study the nuclear matter properties through the di-electron decay of vector mesons produced in pp and NN collisions at kinetic energies from 1-2 GeV/A. Beam Side view from HADESBack view from HADES

3. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 Main Requirements: - Time resolution below 100 ps. - Space resolution around s=3 cm 2. - Working rate: ~600 Hz/cm 2. - Charge measurement for calibration purposes. - Crosstalk as small as possible. RPC WALL GOAL: In high multiplicity experiments a detector is needed to cover the small angle region of the spectrometer for trigger and electron identification purposes: TRIGGER 1: Multiplicity trigger TRIGGER 2: Lepton detection

4. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 A RPC cell Test RPC cell structure 4 gap RPC

5. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 Proposed design: 3 segments per row in 2 layers Side view of some cells Front view Some cells in one sector ~150 cells/300 channels per ~1m 2 sector

6. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 - STEP0: A. Blanco, P. Fonte et al (IEEE Trans. Nucl. Sci. 48(2001)n4, 1249). No longer available components. 1 channel in 2 separated boards. TTL + NIM output. ADC output. - STEP1: 1channel / 2-layers board. Available components. ECL digital output. ADC output. A dead time window of around 1μs is implemented to avoid retriggering of the comparator. This is useful if reflections are present due to, for example, impedance mismatch. - STEP2: 2channels / 4-layers board. Only one digital LVDS output. Time over Threshold (TOT) charge measurement implemented. LVDS output width gives us the TOT, proportionally to RPC signal charge. Tested in ours laboratories. The ESTRELA FEE

7. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 The STEP2 board - 2 channels / 4-layers board (~60x40mm 2 =24cm 2 ). - TOT charge measurement implemented. - One LVDS output signal per channel: Time (leading edge) + Charge (pulse width). - Power consumption ≈ 2.5W/channel (non optimized). - Three voltage regulators: +5V, -5V, +3.3V. PECL-LVDS GATE DIGITAL DELAY FLIP-FLOP REGULATORS COMPARATOR INTEGRATOR PHILIPS AMPLIFIER AGILENT AMPLIFIER

8. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 C C TOT Integrator Amplifiers D Flip-Flop Gate reset PECL- LVDS TOF-Threshold TOT-Threshold In Out Digital Passive Delay OPA655 Wideband Operat. Amplifier (Delay=  s) BGA2712 MMIC Wideband (21dB 1GHz) MSA-0786 Silicon Bipolar MMIC (12.5dB 1GHz) MAX9601-2ch 500ps Propagation Delay MC100EL29-2ch Set/Reset MC10EL05 AND/NAND PTN3311 FEE STEP2 board: One-channel logic C MAX9601-2ch Analog signal Integrated signal Output LVDS signal TOT Threshold

9. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 Laboratory tests We have performed the following tests: 1) The time resolution of the FEE electronics (jitter). 2) The crosstalk between channels. 3) The charge / Time Over Threshold correlation (Q/TOT). Board have been tested in our laboratory with an 600 MHz Agilent 81130A pulser and with a prototype ESTRELA cell.

10. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 STEP2: Jitter Measurement With a 600MHz pulser. With a RPC cell (edge measurement): We illuminate the RPC cell in one of its sides with a 60 Co source. If non electronic time jitter were present, distribution of time differences measured at both edges would show a sharp cut indicating the end of the detector. Electronic jitter smoothens the cut and moves it into a Gaussian tail where the time jitter can be estimated. Cell edge

11. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 STEP2: Crosstalk measurements Crosstalk effects in both channels of the same board have been studied: We measured the ratio of signals in a channel not connected to the RPC induced by its neighbour channel connected to the RPC. Crosstalk in front channel less than 0.5%. Crosstalk in front channel less than 0.5%. Crosstalk in rear channel compatible with 0%. Crosstalk in rear channel compatible with 0%. No explanation for this asymmetry (design effect or accident?). No explanation for this asymmetry (design effect or accident?). No effects observed in the time jitter due to possible fluctuations of the base line.

12. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 STEP2: Q/TOT Behaviour - Good linear behaviour observed with pulse generator. - Poor behaviour observed with real signals (+ some saturation at high Q). - Inaccurate charge selection (scope glitch trigger method). - Not shaping filters careful tuning still done. - Higher thresholds range needed (0-50mV shows to be to small). - But: - Good behaviour has been observed for most signals. - ’Difficult’ events: streamers, avalanches with high ionic tail. TOT width With the prototype cell: Charge (a.u.) TOT width With pulser: V ToT =-30mV Pulse generator amplitude

13. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 The STEP3 board MB DB Motherboard (MB) + Daughterboard (DB) philosophy. - MB (GSI: S. Lange): 31channels / 8-layers board. Regulators, Threshold DACs, Test pulses, Trigger logic. - DB (CIEMAT, USC): 4 channels / 6-layer board (50x45mm 2 =22.5cm 2 ). 2 amplification stages, digitization (LVDS out), Q-TOT implemented, latch enable input comparator is used. (Distances still under study by Hector A. Pol). DB’s MB’s

14. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 FEE STEP3 board: One-channel DB logic 4 ch. out -Amplifier stage (analog stage): - PHILIPS BGA2712 + GALI-S66 (same as FOPI). - Q/TOT stage with TI OPA690. -Digital stage: -Dual MAXIM9601 comparator. Latch enable input used for cut and shape the output pulse. -PECL-LVDS PHILIPS PTN3311 converter. -PHILIPS BFT92 transistor for multiplicity trigger sum. C C TOT Integrator Amplifiers PECL- LVDS TOF-Threshold TOT-Threshold In OPA690 Wideband Operat. Amplifier BGA2712 MMIC Wideband (21dB 1GHz) GALI-S66 Monolithic (18dB 2GHz) MAX9601-2ch 500ps Propagation Delay PTN3311 C Latch enable MAX9601-2ch R 2k2Trigger Out. Σ 4ch. SAMTEC 16 diff. pins BFT92 Wideband PNP Transistor

15. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 Latch Enable configuration Latch Enable is used like another comparator working when two digital levels cross through. MAXIM Comparator Latch Enable TOT Comparator OUT TOF Comparator OUT

16. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 Layout of STEP3 Front layerRear layer - New components: MURATA capacitors and protection diodes.

17. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 -STEP2 features (already tested): -2ch / 4-layer boards of 24cm 2 (2.5W/channel). -Time and charge information together in 1 output/channel. -Electronics Time resolution better than 40ps. -Q/TOT method needs a better tuning. -STEP3 features (boards sent for production): - Motherboard-Daughterboard philosophy. -8 Daughterboards / Motherboard. -4ch / 6-layer Daughterboards of 22.5 cm 2 (1.2W/channel). -Next steps: - April 05: Test at USC with 3 cells prototype. - May 05: Test at LIP with 24 cells prototype. - Nov 05: Test on beam at GSI with a 24 cells prototype. SUMMARY

18. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005

19. The STEP2 2 channels/ 4-layers board (60x40mm 2 ). 2 Stages: 1) A first amplifier stage (analog stage): - PHILIPS amplifier (21dB gain at 1GHz) + - PHILIPS amplifier (21dB gain at 1GHz) + - AGILENT amplifier (12.5dB gain at 1GHZ). - Analog pulse is integrated () On the output we have an integrator stage (TI) to obtain a Q/TOT correlation: we measure the time over threshold of the RPC signal to obtain his charge. On the output we have an integrator stage (TI) to obtain a Q/TOT correlation: we measure the time over threshold of the RPC signal to obtain his charge. 2) A second digital stage, with a dual MAXIM discriminator level (one PECL output for the TOT and other for the TOF measure), a dual ON SEMICONDUCTOR flip-flop, a digital delay line to reset dual flip-flop 1us later, one ON SEMICONDUCTOR gate to obtain the final signal and a PECL-LVDS PHILIPS converter to obtain a LVDS signal proportional to TOF and TOT. We have three voltage: +5V, -5V and 3.3V.

20. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005 Charge Measurement Charge Q is measured loocking at the time the integrated signal is over a given threshold (Q/TOT method) Charge Q is measured loocking at the time the integrated signal is over a given threshold (Q/TOT method) Integrated signal Analog signal Digitized signal Threshold Width C1C1 R3R3 R2R2 R1R1 C2C2 R 1 C 1 : Integration time R 2 C 1 : Decreasing time R 3 C 2 : Overshoot time V TOT threshold tunable between 0 and -50mV

21. Daniel Belver 5. CBM Col. Meeting – GSI. March 11th. 2005

24. PHYSICAL SCENARIO ( URQMD events, AuAu 1 A.GeV ) Rate  =n i /  y.length.s Linear density:  i =n i /  y/N yy n i events N events ii Impact parameter, b=0 RPC