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Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout

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Presentation on theme: "Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout"— Presentation transcript:

1 Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout
Manoel E. de Lima – CIn – UFPE David Harris Harvey Mudd College Spring 2004

2 Outline CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops
Standard Cell Layouts Stick Diagrams 1: Circuits & Layout

3 CMOS Gate Design Activity: Sketch a 4-input CMOS NAND gate
1: Circuits & Layout

4 CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate
1: Circuits & Layout

5 Complementary CMOS Complementary CMOS logic gates
nMOS pull-down network pMOS pull-up network Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON X (crowbar) 1: Circuits & Layout

6 Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON 1: Circuits & Layout

7 Conduction Complement
Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel 1: Circuits & Layout

8 Compound Gates Compound gates can do any inverting function
Ex: A.B+C.D nMOS AB CD 00 01 11 10 1 pMOS nMOS+pMOS 1: Circuits & Layout

9 Example: O3AI Y = (A+B+C).D Vcc 1: Circuits & Layout

10 Signal Strength Strength of signal
How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network 1: Circuits & Layout

11 Pass Transistors Transistors can be used as switches
1: Circuits & Layout

12 Pass Transistors Transistors can be used as switches
1: Circuits & Layout

13 Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well 1: Circuits & Layout

14 Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well 1: Circuits & Layout

15 Tristates Tristate buffer produces Z when not enabled EN A Y 1
1 1: Circuits & Layout

16 Tristates Tristate buffer produces Z when not enabled EN A Y Z 1
Z 1 1: Circuits & Layout

17 Nonrestoring Tristate
Transmission gate acts as tristate buffer Only two transistors\ Noise on A is passed on to Y 1: Circuits & Layout

18 Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule Because we want a Z output 1: Circuits & Layout

19 Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule Because we want a Z output 1: Circuits & Layout

20 Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1
X 1 1: Circuits & Layout

21 Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1
X 1 1: Circuits & Layout

22 Gate-Level Mux Design How many transistors are needed?
1: Circuits & Layout

23 Gate-Level Mux Design How many transistors are needed? 20
1: Circuits & Layout

24 Inverting Mux Inverting multiplexer Pair of tristate inverters
Essentially the same thing Noninverting multiplexer adds an inverter 1: Circuits & Layout

25 Transmission Gate Mux Two transmission gates Only 4 transistors
1: Circuits & Layout

26 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
1: Circuits & Layout

27 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes Or four tristates 1: Circuits & Layout

28 D Latch When CLK = 1, latch is transparent
D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D Transparent latch or level-sensitive latch 1: Circuits & Layout

29 D Latch Design Multiplexer chooses D or old Q 1: Circuits & Layout

30 D Latch Operation 1: Circuits & Layout

31 D Flip-flop When CLK rises, D is copied to Q
At all other times, Q holds its value Positive edge-triggered flip-flop, master-slave flip-flop 1: Circuits & Layout

32 D Flip-flop Design Built from master and slave D latches Master Slave
1: Circuits & Layout

33 D Flip-flop Operation Master on Slave off Master of Slave on
1: Circuits & Layout

34 Race Condition Back-to-back flops can malfunction from clock skew
Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition 1: Circuits & Layout

35 Nonoverlapping Clocks
Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead 1: Circuits & Layout

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