1. 1 Sequential Circuits Dr. Pang

2. 2 Outline Introduction to sequential circuits Basic latch Gated SR latch and gated D latch D flip-flop, T flip-flop, JK flip-flop Register Counter

3. 3 Sequential circuits The outputs depend not only on the present inputs but also on the past behavior of the circuit. Include storage elements The contents of the storage elements represent the state of the circuit The circuit state transitions through a sequence of states

4. 4 The general form of a sequential circuit. Combinational circuit Flip-flops Clock Q W Z Combinational circuit Q1  Q2  Q3 …

5. 5 Basic latch SRQ a Q b 00 01 10 11 No change 01 10 00 (a) Circuit(b) Truth table Q a Q b R S

6. 6 Gated SR latch (a) Circuit Q Q R S R S Clk SR xx 00 01 10 Q(t) (no change) 0 1 Clk 0 1 1 1 111 Qt1+  Q(t) (no change) x (b) Truth table Requires fewer transistors

7. 7 Gated D Latch D Q QClk D 0 1 1 x 0 1 0 1 Qt1+  Qt  (b) Truth table(c) Graphical symbol t 1 t 2 t 3 t 4 Time Clk D Q (d) Timing diagram

8. 8 D Flip-flop D Q Q Clock D Q Q Clear Preset D Q Q Negative-edge DFF Positive-edge with preset and Clear Preset Clear D Q Q Preset and clear: active low; not 0 at same time

9. 9 D Q Q D Q Q D Q Q D Clock Q a Q b Q c Q c Q b Q a Clk D Clock Q a Q b Q c

10. 10 Reset of D flip-flop D Q Q Clear Asynchronous reset Synchronous reset clock clear Q D Q

11. 11 Register A register contains n flip-flops. A flip-flop stores 1-bit information; a register stores n-bit information. Usually a common clock is used for each flip- flop in the register.

12. 12 Shift register D Q Q Clock D Q Q D Q Q D Q Q In Out(n) Q 1 Q 2 Q 3 Q 4 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 Q 1 Q 2 Q 3 Q 4 Out= In Applications: 1) division by 2  shift right by 1bit 2) implement delay elements in DSP In(n) Out(n)=In(n-4) DFF X(n)X(n-1) clock

13. 13 Parallel-shift register Q 3 Q 2 Q 1 Q 0 Clock Parallel input Parallel output Shift/Load Serial input D Q Q D Q Q D Q Q D Q Q

14. 14 Up-Counter Clock Q 0 Q 1 Q 2 Count01235912140 Q 3 4687101113151 Q3 Q2 Q1 Q0 clock

15. 15 Down-counter Clock Q 0 Q 1 Q 2 Count076543210 clock Q2 Q1 Q0

16. 16 Counter with parallel load Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock 1 0 0 0 01234501 Count Q 0 Q 1 Q 2

17. 17 BCD counter Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock 1 0 0 0 Q 3 0 D 3 Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock 0 0 0 Q 3 0 D 3 BCD 0 1 Clear