1. Circuits require memory to store intermediate data
Overview of Chapter 5
Circuits require memory to store intermediate data
Sequential circuits use a periodic signal to determine when to store values.
A clock signal can determine storage times
Clock signals are periodic
Single bit storage element is a flip flop
A basic type of flip flop is a latch
Latches are made from logic gates
NAND, NOR, AND, OR, Inverter
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This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

2. For example, can add two numbers. But:
The story so far ...
Logical operations which respond to combinations of inputs to produce an output.
Call these combinational logic circuits.
For example, can add two numbers. But:
No way of adding two numbers, then adding a third (a sequential operation);
No way of remembering or storing information after inputs have been removed.
To handle this, we need sequential logic capable of storing intermediate (and final) results.

3. Combinational circuit
Sequential Circuits
Combinational circuit
Flip Flops
Outputs
Inputs
Next state
Present state
Timing signal (clock)
Clock
a periodic external event (input)
synchronizes when current state changes happen
keeps system well-behaved
makes it easier to design and build large systems

4. Cross-coupled Inverters
A stable value can be stored at inverter outputs
State 1
State 2

5. S-R latch made from cross-coupled NORs If Q = 1, set state
S-R Latch with NORs
R (reset) Q
S R Q Q’
1 1
1 0
0 1
0 0
0 0 Undefined
1 0 Set
0 1 Reset Q
0 1
S (set)
Stable
1 0
S-R latch made from cross-coupled NORs
If Q = 1, set state
If Q = 0, reset state
Usually S=0 and R=0
S=1 and R=1 generates unpredictable results

6. Latch made from cross-coupled NANDs Sometimes called S’-R’ latch
S-R Latch with NANDs
S R Q Q’ S R Q Q’
0 0
0 1
1 0
1 1
1 1 Disallowed
1 0 Set
0 1 Reset
0 1
Store
1 0
Latch made from cross-coupled NANDs
Sometimes called S’-R’ latch
Usually S=1 and R=1
S=0 and R=0 generates unpredictable results

7. S-R Latches

8. S-R Latch with control input
Occasionally, desirable to avoid latch changes
C = 0 disables all latch state changes
Control signal enables data change when C = 1
Right side of circuit same as ordinary S-R latch.

9. NOR S-R Latch with Control Input
Latch is level-sensitive, in regards to C
Only stores data if C’ = 0 R’ Q C’ Q’
Latch operation enabled by C S’
Outputs change when C is low:
RESET and SET
Otherwise: HOLD
Input sampling enabled by gates

10. Q0 indicates the previous state (the previously stored value)
D Latch
Q0 indicates the previous state (the previously stored value) X S D Q C Q’ R Y
X Y C Q Q’
Q0 Q0’ Store
Reset
Set
Disallowed
X X 0 Q0 Q0’ Store
X 0 Q0 Q0’
D C Q Q’

11. Input value D is passed to output Q when C is high
D Latch X S D Q C Q’ R Y
X 0 Q0 Q0’
D C Q Q’
Input value D is passed to output Q when C is high
Input value D is ignored when C is low

12. Symbols for Latches
SR latch is based on NOR gates
S’R’ latch based on NAND gates
D latch can be based on either.
D latch sometimes called transparent latch

13. Latches are based on combinational gates (e.g. NAND, NOR)
Summary of The D Latch
Latches are based on combinational gates (e.g. NAND, NOR)
Latches store data even after data input has been removed
S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)
With additional gates, an S-R latch can be converted to a D latch (D stands for data)
D latch is simple to understand conceptually
When C = 1, data input D stored in latch and output as Q
When C = 0, data input D ignored and previous latch value output at Q
Next time: more storage elements!
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

14. What if the output only changed on a C transition?
Clocking Event
What if the output only changed on a C transition? C D Q Q’
X 0 Q0 Q0’
D C Q Q’
Positive edge triggered
Lo-Hi edge
Hi-Lo edge

15. Master-Slave D Flip Flop
Consider two latches combined together
Only one C value active at a time
Output changes on falling edge of the clock

16. Stores a value on the positive edge of C
D Flip-Flop
Stores a value on the positive edge of C
Input changes at other times have no effect on output C D Q Q’
X 0 Q0 Q0’
D C Q Q’
Positive edge triggered
D gets latched to Q on the rising edge of the clock.

17. Clocked D Flip-Flop
Stores a value on the positive edge of C
Input changes at other times have no effect on output

18. Positive and Negative Edge D Flip-Flop
D flops can be triggered on positive or negative edge
Bubble before Clock (C) input indicates negative edge trigger
Lo-Hi edge
Hi-Lo edge

19. J -> set, K -> reset, if J=K=1 then toggle output
Clocked J-K Flip Flop
Two data inputs, J and K
J -> set, K -> reset, if J=K=1 then toggle output
Characteristic Table

20. Asynchronous Inputs
J, K are synchronous inputs
Effects on the output are synchronized with the CLK input.
Asynchronous inputs operate independently of the synchronous inputs and clock
Set the FF to 1/0 states at any time.

21. Asynchronous Inputs

22. Asynchronous Inputs
Note reset signal (R) for D flip flop
If R = 0, the output Q is cleared
This event can occur at any time, regardless of the value of the CLK

23. Parallel Data Transfer
Flip flops store outputs from combinational logic
Multiple flops can store a collection of data

24. Designing Finite State Machine
Understanding flip flop state:
Stored values inside flip flops
Clocked sequential circuits:
Contain flip flops
Representations of state:
State equations
State table
State diagram
Finite state machines
Mealy machine
Moore machine
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

25. Present state indicates current value of flip flops
State Table
Sequence of outputs, inputs, and flip flop states enumerated in state table
Present state indicates current value of flip flops
Next state indicates state after next rising clock edge
Output is output value on current clock edge
0 0
0 1
1 0
1 1
Present
State
Next State
x=0 x=1
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
Output
State Table

26. All possible input combinations enumerated
State Table
All possible input combinations enumerated
All possible state combinations enumerated
Separate columns for each output value.
Sometimes easier to designate a symbol for each state.
Present
State
Next State
x=0 x=1
s s
s s
s s
s s
Output s0 s1 s2 s3
Let:
s0 = 00
s1 = 01
s2 = 10
s3 = 11

27. Output based on state and present input
Mealy Machine
Output based on state and present input
Comb.
Logic
Comb.
Logic
Q(t+1)
Flip
Flops
next
state
Q(t)
Y(t)
present
state
X(t)
present
input
clk

28. Moore Machine
Output based on state only
Comb.
Logic
Comb.
Logic
Q(t+1)
Y(t)
Flip
Flops
next
state
Q(t)
present
state
X(t)
present
input
clk

29. Mealy versus Moore

30. State Diagram with One Input & One Mealy Output
Mano text focuses on Mealy machines
State transitions are shown as a function of inputs and current outputs.
e.g. 1
0/0
Input(s)/Output(s) shown in transition
1/1 S1
1/0 S4 S2
0/0
0/0
0/0
1/0 S3
1/0

31. State Diagram with One Input & a Moore Output
Moore machine: outputs only depend on the current state
Outputs cannot change during a clock pulse if the input variables change
Moore Machines usually have more states.
No direct path from inputs to outputs
Can be more reliable

32. Clocked Synchronous State-machine Analysis – next class
Given the circuit diagram of a state machine:
Analyze the combinational logic to determine flip-flop input (excitation) equations: Di = Fi (Q, inputs)
The input to each flip-flop is based upon current state and circuit inputs.
Substitute excitation equations into flip-flop characteristic equations, giving transition equations: Qi(t+1) = Hi( Di )
From the circuit, find output equations: Z = G (Q, inputs)
The outputs are based upon the current state and possibly the inputs.
Construct a state transition/output table from the transition and output equations:
Similar to truth table.
Present state on the left side.
Outputs and next state for each input value on the right side.
Provide meaningful names for the states in state table, if possible.
Draw the state diagram which is the graphical representation of state table.

33. Concept of the State Machine
Computer Hardware = Datapath + Control
Qualifiers
Registers
Combinational Functional
Units (e.g., ALU)
Busses
FSM generating sequences
of control signals
Instructs datapath what to
do next
Control
Control
State
Qualifiers
and
Inputs
Control
Signal
Outputs
Datapath

34. Designing Finite State Machines
Specify the problem with words
(e.g. Design a circuit that detects three consecutive 1 inputs)
Assign binary values to states
Develop a state table
Use K-maps to simplify expressions
Flip flop input equations and output equations
Create appropriate logic diagram
Should include combinational logic and flip flops

35. Example: Detect 3 Consecutive 1 inputs
State S0 : zero 1s detected
State S1 : one 1 detected
State S2 : two 1s detected
State S3 : three 1s detected
Note that each state has 2 output arrows
Two bits needed to encode state

36. State Table for Sequence Detector
Present
State
Sequence of outputs, inputs, and flip flop states enumerated in state table
Present state indicates current value of flip flops
Next state indicates state after next rising clock edge
Output is output value on current clock edge
Next
State
Input
Output
A B x A B y
S0 = 00
S1 = 01
S2 = 10
S3 = 11

37. Finding Expressions for Next State and Output Value
Create K-map directly from state table (3 columns = 3 K-maps)
Minimize K-maps to find SOP representations
Separate circuit for each next state and output value

38. Circuit for Consecutive 1s Detector
Note location of state flip flops
Output value (y) is function of state
This is a Moore machine.

39. Concept of the State Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Symbolic State Transition Table
State
Diagram
Encoded State Transition Table
Note: Present state and output are the same value
Moore machine

40. Concept of the State Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D FF Implementation
Timing Behavior: Input

41. Mealy and Moore Machines
Solution 1: (Mealy)
0/0
Even
Odd
1/1
1/0
0/1 1
Reset
[0]
[1]
Output
Input
Transition
Arc
Output is
dependent only
on current state
O/P is dependent
on current state and
input in Mealy
Solution 2: (Moore)
Mealy Machine: Output is associated with the state transition
- Appears before the state transition is completed (by the next clock pulse).
Moore Machine: Output is associated
with the state
Appears after the state transition
takes place.

42. Step 1. Specify the problem
Vending Machine FSM
Step 1. Specify the problem
Deliver package of gum after 15 cents deposited
Single coin slot for dimes, nickels
No change
Design the FSM using combinational logic and flip flops

43. Vending Machine FSM
State Diagram
Reuse states
whenever possible
Symbolic State Table

44. How many flip-flops are needed?
Vending Machine FSM
State Encoding
How many flip-flops are needed?

45. Determine F/F implementation
Vending Machine FSM
Determine F/F implementation
K-map for Open
K-map for D0
K-map for D1
Q1 Q0
D N Q1 Q0 D N

46. Minimized ImplementationQ1 D1 Q1 D
D Q Q0
CLK R Q N
OPEN
Reset N Q0 D0 Q0
D Q
CLK Q1 R Q N
Reset Q1 D
Vending machine FSM implementation based on D flip-flops(Moore).

47. Finite state machines form the basis of many digital systems
Summary
Finite state machines form the basis of many digital systems
Designs often start from clear specifications
Develop state diagram and state table
Optimize using combinational design techniques
Mealy or Moore implementations possible
Can model approach using HDL.
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.