1. Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.

2. Sequential Circuits New output are dependent on the inputs and the preceding values of outputs. Characteristic: output nodes are intentionally connected back to inputs. Basic sequential circuits: – Level Sensitive Circuits – Edge Sensitive Circuits

3. Small Perturbation to a Basic Inverter

4. Large Perturbation to a Basic Inverter

5. Application: SRAM

6. Metastable Point

7. Small Perturbation from the Metastable Point

8. Intel’s Random Bit Generator

9. Latches Latches are level sensitive. Latches propagate values from input to output continuously. S sets Q =1; R sets Q=1 – Active low inputs are enabled by 0s. – Active high inputs are enabled by 1s.

10. SR Latch with NOR Gates t PDSQ =2 NOR gate delays. t PDRQ_ =1 NOR gate delay Forbidden State SR are trigger pulses which can return to zero once Q is set. Active High inputs

11. SR Latch with NAND Gates Active low inputs

12. D Latch

13. D-latch Operation

14. D-Latch (CK=0) 0 D DB 0 0

15. D-Latch (CK=1) 1 D DB D D

16. Analyze D Latch Using Boolean Algebra

17. Transistor Level Implementation of D-Latch

18. D-Latch (CLK=1,D=1) VDD 0

19. Standard Library D Latch CLK=VDD (Q=D)

20. Standard Library D Latch CLK=0V (Hold State)

21. JK Flip-Flop

22. JK Flip Flop (CK=0) 0 1 1

23. JK Flip Flop (CK=1,J=K=0) 1 1 1 0 0

24. JK Flip Flop (CK=1,J=K=1) 1 1 1 If CK is on for a long time, the output of this JK flip flip will toggle! The pulse width of CK must be less than the propagation delay time through the loop.

25. JK Flip Flop (CK=1,J=0→1,K=0) 1 1 0 1 0

26. 1 1 0 1 0

27. CK=1, J=0 → 1, K=0 Regardless of initial value of Q, – CK=1, J= → 1, K=0 will set the updated value of Q to a 1.

28. JK Flip Flop (CK=1,J=0,K= 0→ 1) 1 1 0 1 0

29. 1 1→0 →1 0 1 0

30. CK=1, J=0, K=0 → 1 Regardless of initial value of Q, – CK=1, J= 0, K=0 → 1 will set the updated value of Q to a 0.

31. JK Flip-Flop J=1, K=1 can lead to oscillation if the width of CK is longer than propagation delay.

32. JK Master-Slave Flip-Flop 1 0 1 1 The slave latch is insulated from changes of J and K when CK=1 Q holds its current value. The Q of the master latch is updated when CK=1.

33. JK Master-Slave Flip-Flop (CK=1) 1 0 1 1 JK 00

34. 1 0 1 1 JK 11 1 1

35. 1 0 1 1 JK 01 0 1

36. 1 0 1 1 JK 10 1 0

37. JK 00 11 01 10

39. JK 00 10 00 If J catches a glitch, it is stuck the master latch! 1 0

40. Edge Sensitive Circuits

41. JK Negative Edge-Triggered Flip-Flop 1 Active-Low Devices 1 1 Disabled “hold” mode

42. JK Negative Edge-Triggered Flip-Flop 0 1 1 Active-Low Devices 1 1 “hold” mode enabled

43. JK Negative Edge-Triggered Flip-Flop 1 1 “hold” mode enabled →disabled

44. JK Negative Edge-Triggered Flip-Flop CK The NAND latch is only updated for a short interval immediately after the negative edge, before being set to the hold.

45. Update JnJn KnKn Q n+1 0011 011 11 101

46. J=0; K=1 JnJn KnKn Q n+1 0110 0110 011

47. J=1; K=0 JnJn KnKn Q n+1 10Q11 01Q n =0 S=0 11 01Q n =1 S=1 1Q n =1 Q n+1 =1

48. Negative Edge Triggered Flip-FLop JnJn KnKn Q n+1 0011 0110 11 10Q11

49. D Flip-Flop

50. D-Flop 1 2 CK of latch 2 CK of latch 1 X OUT=X X=IN 1: Hold 2: Track 2:hold 1:track OUT samples IN at the positive edge of the clock

51. Timing Diagram

52. Definition Setup time: the time that the incoming data must be stable before the clock arrives Hold time: the length of time that the data remains stable after the clock arrives for proper operation If the data is stable before the setup time and continues to be stable after the hold time, the flop will work properly. If the data arrives within the period designated by the setup and hold times, the flop may or may not capture the correct value.

53. CLK-Q The delay from the time that the clock arrives to the point that the output stabilizes. In reality the data must arrive at the setup time before the clock hits and the output is valid after the CLK-Q delay.