1. Class presentation based on ISSCC 2013- 24.5 : A Low-power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS By Paul N.Whatmough, Shidhartha Das, David M,Bull ARM, Cambridge, United Kingdom Presented by: 1 Mahnaz Rasti 1 Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran Spring 2013 1

2. Outline : Razor Systems ANT(Algorithmic Noise Tolerance) Circuits Combining Technologies Architecture of the Chip 2

3. Outline: Razor Systems ANT(Algorithmic Noise Tolerance) Circuits Combining Technologies Architecture of the Chip 2

4. Razor Systems: 4

5. Razor propose a new approach to DVS, based on dynamic detection of circuit timing errors Key Idea: Tune the supply voltage by monitoring the error rate during circuit operations [1] [1] (MICRO-36), December 2003 - Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation- Dan Ernst 5

6. Razor Systems(ex. flip-flop [1] ) Double samples pipeline stages value Once with a fast clock Again with a time borrowing delay clock A metastability-tolerant comparator then validates latch value sampled with fast clock In the case of a timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. [1] Ref: (MICRO-36), December 2003 - Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation- Dan Ernst 6

7. Razor Systems: Figure 1. Pipeline augmented with Razor latches and control lines. Ref:(MICRO-36), December 2003 - Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation- Dan Ernst 7

8. Outline: Razor Systems ANT(Algorithmic Noise Tolerance) Circuits Combining technologies Architecture of the Chip 8

9. ANT Circuits: Figure 2 Ref: http://icims.csl.uiuc.edu/~vips 9

10. ANT Circuits: Modify algorithm for system level error control ANT detects such errors in system output and mitigates their effects on system performance. Errors are detected by low complexity prediction scheme. Figure 3 Ref:http://icims.csl.uiuc.edu/~vips 10

11. ANT Circuits: Figure 4 : Error predictor in ANT Circuits-[http://icims.csl.uiuc.edu/~vips] 11

12. Outline: Razor Systems ANT(Algorithmic Noise Tolerance) Circuits Combining technologies Architecture of the Chip 12

13. :Combining technologies Razor Systems Low power, fault tolerant ANT Rely on imbalance ripple adder and hence limited clock frequency, increasing baseline area and power & High clock frequency Low overheads 13

14. Outline: Razor Systems ANT(Algorithmic Noise Tolerance) Circuits Combining technologies Architecture of the Chip 14

15. Architecture of the Chip Approximate Error Correction Time Borrow Tracking Figure5: FIR accelerator with Razor latches, time-borrow tracking (TBT) and approximate error correction (AEC)- ISSCC 2013 – 24.5 15

16. Architecture of the Chip Figure6: FIR accelerator with Razor latches, time-borrow tracking (TBT) and approximate error correction (AEC)- ISSCC 2013 – 24.5 16

17. Characteristics: Tow distinct error correction technique TBT AEC A 1Ghz datapath due to elimination of ripple-carry adders Energy efficiency improvement of up to 37% 17

18. Die: TSMC CMOS 65nm LPTechnology Node 530 micron * 350 micronDimension 16-Tap FIR, 8b coefficient, 18b o/pPipeline Design 1974(393 in pipeline)/ 120 (30% of pipeline FF) Total FF/RZL 1.59%Hold Buffer Area Overhead 1.008 GHz @ 1.2v with RazorMax Clock Frequency Figure7: Die photo- ISSCC 2013 – 24.5 18

19. References: 1.ISSCC 2013 – 24.5 – “A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS” - Paul N. Whatmough - ARM, Cambridge, United Kingdom. 2.(MICRO-36), December 2003 – “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation”- Dan Ernst 3.“Algorithmic Noise Tolerance for Low Power Signal Processing in the Deep SubMicron Area” - ECE Department University of Illinois at Urbana- Champaign 19