1. Embedded System Design, Spring 2012 DataPath Engine Group Project Matt Slowik Porting DPE to Xilinx FPGA environment, Component Integration

2. test_dpe_top.v dpe_top.v DP RQS QS CTL top.v driver User application top_debug.v Xilinx ISE Behavioral Simulation FPGA ARM Design Structure ROM 1024x22 Ucode 256x96

3. Simulation Results UCODE burned from wcs.data, ROM from rom.data Using tsmc.v and udp.v (translated user defined primitives to modules)

4. Implementation Results – Data Channel read from ARM, FPGA PNR Statistics (Frequency) IT WORKS!!! Lesson Learned – carefully parse warnings. The “optimizer” will destroy large logic cones if not careful (proper initialization) even though simulation passes. Could run at 10MHz… (SYS_CLK = 26MHz. Made custom clock) I am running at 6.5MHz for easy PNR.

5. BUGS SQUASHED - UCODE Block RAM not working. The burn in values are wrong. They start at entry 0 instead of entry 1 and even some entries have the wrong values. Wrote a script to create a latch array with correct values and offsets. - ROM Block is not burned in correctly. Rom.data has first entry at index 2 and not index 0. Had to tweak wrapper to get it to work correctly. - Hold cells in FIFO, DP_MUX4, DP_MUX48 modules. Case where behavioral/implementable verilog differs (no trireg elements) <= Had to recode. Also case in poor communication - No delay elements (#) in Xilinx. They are ignored. Recoding required mostly in CTL blocks and the test wrapper. - User Designed Primitives – Many bugs that were very tedious to find (had to translate verilog tables into implementable design. - Xilinx ISE not as “lax” as modelsim. Issues with the netlister and port naming formats unreadable by Xilinx (particularly in DP module). LESSONS LEARNED Wasted a lot of timing fine tuning Behavioral model.. Only to find out it wasn’t implementable. Need to keep IMPLEMENTATION mindset from the beginning.