1. Seminar at University of Geneva, November 6 th, 2013 1 Monolithic pixel sensors Ivan Perić

2. Seminar at University of Geneva, November 6 th, 2013 Introduction – classification of CMOS sensors 2 Pixel type Simple pixels (no particle detection in pixel, analog output, rolling shutter readout) Intelligent pixels (particle detection in pixel, digital output, zero-suppressed readout) Technology Standard (CMOS, Opto- or HV-CMOS) or special technology (Hi-resistive CMOS, backside depleted, SOI) Bias voltage Low (charge collection: diffusion based, sensor: epi layer) High (charge collection: drift based, sensor: depleted layer)

3. Seminar at University of Geneva, November 6 th, 2013 Introduction – classification of CMOS sensors 3 Simple pixels CMOS pixel sensors Standard MAPS Intelligent pixels INMPAS TWELL MAPS Depleted MAPS with intelligent pixels HVCMOS (Hi-Res CMOS included) Espros MAPS T3 MAPS SOI LV MAPS (Epi Layer) HV MAPS (Delpeted Layer) Standard (HV-) or Opto- CMOS Standard MAPS (“MIMOSA- type”) TWELL MAPS HVCMOS, T3 Special technologyINMAPSSOI, Espros

4. Seminar at University of Geneva, November 6 th, 2013 4 Commercial CMOS monolithic pixel sensors

5. Seminar at University of Geneva, November 6 th, 2013 CMOS monolithic sensors The original application of CMOS sensors – consumer electronics Imaging sensors for digital cameras and mobile phones Improvements are necessary for HEP Phone with 41 M pixel sensor, 1.4um pixel size

6. Seminar at University of Geneva, November 6 th, 2013 Commercial imaging sensors Imaging sensors for digital cameras and mobile phones Canon 120 M pixels CMOS, 2 µm pixel size 29 mm

7. Seminar at University of Geneva, November 6 th, 2013 MOS technology MOS Technology – Integrated circuit technology based on Metal Oxide Semiconductor field effect transistors Silicon p type n type region “diffusion” „Metal“ ElectrodeInsulator Samsung 32nm process

8. Seminar at University of Geneva, November 6 th, 2013 PN junction The simplest building element – PN junction N-diffusion – potential minimum for electrons P-substrate –potential barrier for electrons Silicon n typeSilicon p type Free electrons

9. Seminar at University of Geneva, November 6 th, 2013 PN junction Reversely biased – large depleted layer Detector mode Silicon n typeSilicon p type + Depleted

10. Seminar at University of Geneva, November 6 th, 2013 PN junction as sensor of radiation PN junction as sensor 1. step - ionization Atoms Photons or particles Ionisation Free e-

11. Seminar at University of Geneva, November 6 th, 2013 PN junction as sensor of radiation PN junction as sensor 2. step – charge collection Two possibilities for charge collection – drift (through E-force) and by diffusion (density gradient) Atoms Collection of electrons

12. Seminar at University of Geneva, November 6 th, 2013 PN junction as sensor of radiation PN junction as sensor 3. step – charge to voltage conversion Collection of the charge signal leads to the potential change AtomsPotential change

13. Seminar at University of Geneva, November 6 th, 2013 CMOS pixel Pixel sensor in MOS technology N-type region Diffusion (shallow) Or well (deep) Sensor-junction MOS FET Sensor-junction MOS FET Gate

14. Seminar at University of Geneva, November 6 th, 2013 CMOS pixel N in P diode acts as sensor element – signal collection electrode N-type region Diffusion (shallow) Or well (deep) Sensor-junction MOS FET Sensor-junction MOS FET Gate

15. Seminar at University of Geneva, November 6 th, 2013 CMOS pixel Charge generated by ionization is collected by the N-diffusion This leads to the potential change of the N-diffusion The potential change is transferred to transistor gate – it modulates the transistor current N-type region Diffusion (shallow) Or well (deep) Sensor-junction MOS FET Sensor-junction MOS FET Gate

16. Seminar at University of Geneva, November 6 th, 2013 Rolling shutter readout Readout principle: Many pixels (usually one row) share one readout line Additional MOSFET used as switch The readout lines are connected to the electronics at the chip periphery that does signal processing A AAAAA Switch Pixel i+1 Pixel i Periphery of the chip

17. Seminar at University of Geneva, November 6 th, 2013 17 CMOS monolithic pixel sensors for particle tracking

18. Seminar at University of Geneva, November 6 th, 2013 CMOS sensors for particle tracking Can CMOS structure be used for detection of high energy particles in particle tracking? Yes, but fill factor is an issue – ratio of the sensitive versus insensitive area DetectedNot detected Charge collection by drift Absorbed by electronics

19. Seminar at University of Geneva, November 6 th, 2013 Fill-factor Partial signal collection in the regions without E-field

20. Seminar at University of Geneva, November 6 th, 2013 Fill-factor Partial signal collection in the regions without E-field Recombination

21. Seminar at University of Geneva, November 6 th, 2013 Overview Partial signal collection in the regions without E-field Recombination

22. Seminar at University of Geneva, November 6 th, 2013 Overview Partial signal collection in the regions without E-field Charge collection by diffusion

23. Seminar at University of Geneva, November 6 th, 2013 Fill-factor Partial signal collection in the regions without E-field Charge collection by diffusion

24. Seminar at University of Geneva, November 6 th, 2013 Fill-factor In the case visible light imaging, the insensitive regions do not impose a serious problem Light can be focused by lenses Exposure time can be increased In the case of particle tracking, any insensitive region should be avoided

25. Seminar at University of Geneva, November 6 th, 2013 CMOS pixel sensor with 100% fill factor MOS sensor with 100% fill-factor Based on epi-layer Monolithic active pixel sensor - “MAPS” Lightly p-doped epi-layer Heavily p-doped P-well N-diffusion or N-well MOS FET NMOS

26. Seminar at University of Geneva, November 6 th, 2013 CMOS pixel sensor with 100% fill factor Ionization in the epi-layer Charge collection by diffusion N-diffusion or N-well Particle

27. Seminar at University of Geneva, November 6 th, 2013 27 MAPS

28. Seminar at University of Geneva, November 6 th, 2013 28 CMOS pixel sensor with 100% fill factor - MAPS MAPS NMOS transistor in p-wellN-well (collecting region) Pixel i Charge collection (diffusion) P-type epi-layer P-type substrateEnergy (e-)

29. Seminar at University of Geneva, November 6 th, 2013 MAPS Many institutes are developing MAPS, for instance: IPHC Strasbourg (PICSEL group) Family of MIMOSA chips Applications:, STAR-detector (RHIC Brookhaven), Eudet beam-telescope and ALICE inner tracker upgrade http://www.iphc.cnrs.fr/Monolithic-Active-Pixel-Sensors.html

30. Seminar at University of Geneva, November 6 th, 2013 MAPS http://www.iphc.cnrs.fr/Monolithic-Active-Pixel-Sensors.html Ultimate chip for STAR MIMOSA 26 for Eudet telescope MIMOSAs are based on rolling shutter RO but use more complex pixel electronics Continuous reset and double correlated sampling

31. Seminar at University of Geneva, November 6 th, 2013 Charge collection & technology studies – simple demonstrators Production Real size prototype - yield studies Reticule 2x 2 cm 2006 Data compression - digitization Sara 2006Suze 2007 Final circuits – sub-blocs integration Mimosa22 2008 Pixel Array Discriminators Zero Suppression BiasReadout 2007 1999 MAPS

32. Seminar at University of Geneva, November 6 th, 2013 32 Advanced CMOS pixel sensors with intelligent pixels

33. Seminar at University of Geneva, November 6 th, 2013 33 Frame readout - Simple pixels - Signal and leakage current is collected - No time information is attached to hits - The whole frames are readout Small pixels Low power consumption Slow readout

34. Seminar at University of Geneva, November 6 th, 2013 34 Sparse readout 6 9 9 3 6 9 9 3 - Intelligent pixels - FPN is tuned inside pixels - Leakage current is compensated - Hit detection on pixel level - Time information is attached to hits  Larger pixels  Larger power consumption Fast (trigger based) readout

35. Seminar at University of Geneva, November 6 th, 2013 35 Intelligent pixel LatchComparatorCR-RC 4-bit tune DAC Readout bus CSA Bus driver RAM

36. Seminar at University of Geneva, November 6 th, 2013 36 Sparse readout Rolling shutter readout Reset Comp. out Sensor RO enable Comp. out Sensor

37. Seminar at University of Geneva, November 6 th, 2013 CMOS electronics Two transistor types n-channel NMOS and p-channel PMOS are needed for the realization of complex circuits Silicon p type Silicon n type „Metal“ Electrode Insulator Silicon n type Silicon p type „Metal“ Electrode Insulator NMOSPMOS NMOS PMOS Free e- Holes

38. Seminar at University of Geneva, November 6 th, 2013 CMOS electronics Example: A good voltage amplifier can only be realized with CMOS Silicon p type Silicon n type „Metal“ Electrode Insulator Silicon n type Silicon p type „Metal“ Electrode Insulator NMOSPMOS NMOS PMOS Free e- Holes

39. Seminar at University of Geneva, November 6 th, 2013 MAPS structure with CMOS pixel electronics If PMOS transistors are introduced, signal loss can happen NMOS transistor in p-well N-well (collecting region) Pixel i P-type epi-layer P-type substrateEnergy (e-) MAPS with a PMOS transistor in pixel PMOS transistor in n-well Signal collection Signal loss

40. Seminar at University of Geneva, November 6 th, 2013 40 Advanced structures: INMAPS

41. Seminar at University of Geneva, November 6 th, 2013 41 INMAPS NMOS shielded by a deep p-well PMOS in a shallow p-well N-well (collecting region) Pixel P-doped epi layer INMPAS Deep P-layer is introduced to shield the PMOS transistors from epi layer No charge loss occurs This is not a CMOS standard process Only one producer so far: Tower Jazz

42. Seminar at University of Geneva, November 6 th, 2013 Overview INMAPS Tower Jazz process is gaining popularity in particle physics community /ALICE inner tracker) It was originally developed by the foundry and the Detector Systems Centre, Rutherford Appleton Laboratory 2 Megapixels, large area sensor Designed for high-dynamic range X-ray imaging 40 µm pixel pitch 1350 x 1350 active pixels in focal plane Analogue readout Region-of-Reset setting 140 dB dynamic range 20 frames per second FORTIS chip http://dsc.stfc.ac.uk/Capabilities/CMOS+Sensors+Design/Follow +us/19816.aspx

43. Seminar at University of Geneva, November 6 th, 2013 Overview Detector Systems Centre, Rutherford Appleton Laboratory – some examples http://dsc.stfc.ac.uk/Capabilities/CMOS+Sensors+Design/Follow +us/19816.aspx Wafer scale 120 x 145 mm chip for medical imaging

44. Seminar at University of Geneva, November 6 th, 2013 44 TWELL - MAPS

45. Seminar at University of Geneva, November 6 th, 2013 45 TWELL MAPS Triple-well MAPS Deep n-well2. n-well P-well NMOSPMOS Pixel Epi-layer Diffusion Energy (e-) Signal lossSignal collection Collection electrode is a deep n-well To avoid crosstalk, secondary n-well is used for digital electronics Rely on diffusion, implemented in low voltage CMOS processes Collaboration: INFN Pisa, Pavia, Trieste, Padova, Torino, Bologna

46. Seminar at University of Geneva, November 6 th, 2013 46 TWELL MAPS APSEL Chips for B-factories The APSEL4D MAPS chip bonded to the chip carrier. Schematic drawing of the full Layer0 made of 8 pixel modules mounted around the beam pipe with a pinwheel arrangement. “Thin pixel development for the SuperB silicon vertex tracker”, NIMA vol. 650, 2011

47. Seminar at University of Geneva, November 6 th, 2013 47 Fast CMOS detectors based on drift charge collection: detectors in HVCMOS-processes and the CMOS processes with a high resistive wafer

48. Seminar at University of Geneva, November 6 th, 2013 48 Drift based detector: HVMAPS HVMAPS rely on the charge collection by drift Fast charge collection – high radiation tolerance The key is the use of a high voltage n-well in a relatively highly doped substrate Pixel electronics is embedded in the n-well Two concepts: High Ohmic Monolithic Pixels - LePIX – relies on a special CMOS process with high resistive substrate (CERN, Geneve) HVCMOS (or smart diode arrays - SDAs) – use a commercial HVCMOS process

49. Seminar at University of Geneva, November 6 th, 2013 49 HVCMOS detectors (smart diode arrays)

50. Seminar at University of Geneva, November 6 th, 2013 50 P-Substrate Depleted “Smart” Diode n-Well Pixel “Smart diode” Detector DriftEnergy (e-) Smart diode array SDA

51. Seminar at University of Geneva, November 6 th, 2013 SDA Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier – placed in the n-well. PMOS N-well NMOS DS G holes electrons P-well P-substrate

52. Seminar at University of Geneva, November 6 th, 2013 SDA Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier – placed in the n-well. P-substrate

53. Seminar at University of Geneva, November 6 th, 2013 SDA P-substrate Collected charge causes a voltage change in the n-well. This signal is sensed by the amplifier – placed in the n-well.

54. Seminar at University of Geneva, November 6 th, 2013 54 Intelligent pixel ComparatorCR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

55. Seminar at University of Geneva, November 6 th, 2013 55 Intelligent pixel ComparatorCR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

56. Seminar at University of Geneva, November 6 th, 2013 56 Intelligent pixel ComparatorCR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

57. Seminar at University of Geneva, November 6 th, 2013 57 Intelligent pixel Comparator CR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

58. Seminar at University of Geneva, November 6 th, 2013 58 Intelligent pixel Comparator CR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

59. Seminar at University of Geneva, November 6 th, 2013 59 Intelligent pixel Comparator CR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

60. Seminar at University of Geneva, November 6 th, 2013 60 Intelligent pixel Comparator CR-RC CSA N-well AC coupling 3.3 V -50 V P-substrate

61. Seminar at University of Geneva, November 6 th, 2013 3D layout of a “smart diode” 40 µm 3D layout generated by GDS2POV software

62. Seminar at University of Geneva, November 6 th, 2013 Applications Mu3e experiment at PSI and ATLAS upgrade option 5 mm 62 Mu3e prototype chip 4.4mm ATLAS prototype chip

63. Seminar at University of Geneva, November 6 th, 2013 63 Special monolithic technologies

64. Seminar at University of Geneva, November 6 th, 2013 Espros 64 N-type P-diffusion Depleted Ohmic connection P-well N-well Espros – semiconductor company in Switzerland

65. Seminar at University of Geneva, November 6 th, 2013 Espros 65 HV N-type depleted N-well P-diffusion No ohmic connection P-well

66. Seminar at University of Geneva, November 6 th, 2013 Espros 66 P-well N-well HV N-type depleted P-diffusion

67. Seminar at University of Geneva, November 6 th, 2013 T3-MAPS 67 P-well T3-well P-substrate T3-MAPS rely on a special option in IBM 130nm technology

68. Seminar at University of Geneva, November 6 th, 2013 68 Thank you!