S02 - Digital Logic Required: PM: Ch 2, pgs 5-25

Name: S02 - Digital Logic Required: PM: Ch 2, pgs 5-25
Uploaded: 2017-08-11T00:49:20+00:00
Duration: PTM54S32
Channel: Dwight Winsett
Description: S02 - Digital Logic Required: PM: Ch 2, pgs 5-25

S02 - Digital Logic Required: PM: Ch 2, pgs 5-25
Code: Chs Wiki: Finite State Machine Recommended: Transistors and Faucets Gates, Tables, Expressions Combinational Logic Sequential Logic Paul Roper

CS 224 Chapter Project Homework S00: Introduction
Unit 1: Digital Logic S01: Data Types S02: Digital Logic L01: Warm-up L02: FSM HW01 HW02 Unit 2: ISA S03: ISA S04: Microarchitecture S05: Stacks / Interrupts S06: Assembly L03: Blinky L04: Microarch L05b: Traffic Light L06a: Morse Code HW03 HW04 HW05 HW06 Unit 3: C S07: C Language S08: Pointers S09: Structs S10: I/O L07b: Morse II L08a: Life L09a: Snake HW07 HW08 HW09 HW10 BYU CS 224 Digital Logic

Digital Logic Learning Outcomes…
Students will be able to: Use transistors to create an invertor, OR, and/or AND gate. Convert a logical equation to a truth table or digital gates. Convert a truth table to digital gates or a logical equation. Convert digital gates to a logical equation or a truth table Use combinational logic to create any logical device (logical completeness). Create computer memory using sequential logic. Use a finite state machine in a practical application. BYU CS 224 Digital Logic

Topics to Cover… Logical and Arithmetic Operations
Digital Logic Devices The Transistor Devices: Inverter, NAND, NOR, Drivers Gates, Truth Tables, and Equations Equations De Morgan’s Law Translations Boolean Algebra Combinational Logic devices Decodes, Multiplexors, Adders, PLAs Logical Completeness Sequential Logic Latches Memory Finite State Machine Turing Machine BYU CS 224 Digital Logic

Logical and Arithmetic Operations

Logical Operations 1 1 1 1 1 1 1 1 NOT – Logical complement
B NOT A A OR B A NOR B A AND B A NAND B A XOR B 1 1 1 1 1 1 1 1 NOT – Logical complement OR, NOR – Logical disjunction AND, NAND – Logical conjunction XOR – Exclusive OR, A OR B, but not both OR 0111 AND 0111 XOR 0111 Bitwise: BYU CS 224 Digital Logic

Arithmetic Operations
- + -1 1 -2 2 -3 3 -4 4 -5 5 -6 6 -7 7 -8 ADD – Summation, commutative and associative SUB – Difference, neither commutative nor associative NEG – Additive inverse 1010 (-6) (-6) ADD 0111 (7) SUB 0111 (7) NEG 0111 (7) 0001 (1) (3) (-7) Bitwise: BYU CS 224 Digital Logic

Logical/Arithmetic Operations
Quiz 2.1 What are the results of the following 4-bit bitwise logical operations? NOT OR NOR AND NAND XOR What are the results of the following 4-bit arithmetic operations (2’s complement)? NEG ADD SUB BYU CS 224 Digital Logic

The Transistor

The Transistor Semiconductors A semiconductor is a material which has electrical conductivity properties of a metal (such as copper) and that of an insulator (such as glass). Semiconductors are the foundation of modern solid state electronics. BYU CS 224 Digital Logic

History of the Transistor
Around 1945, Bell Labs scientists discovered that silicon was comprised of two distinct regions differentiated by the way in which they favored current flow. The area that favored positive current flow they named "p" and the area that favored negative current flow they named "n". The transistor effect describes the change from a condition of conductivity (switched “on”, full current flow) to a condition of insulation (switched “off”, no current flow). BYU CS 224 Digital Logic

Digital Logic Circuits
The Transistor Digital Logic Circuits Computers = large number of simple structures Intel 4004 = 2,300 transistors Intel Pentium 4 = 42 million transistors Intel Core 2 Duo = 291 million transistors Intel i7 “Bloomfield” = 731 million transistors BYU CS 224 Digital Logic

Moore’s Law The Transistor 2010’s 2000’s 1990’s 1980’s 1970’s 1960’s
Gordon E. Moore 1960’s 1970’s 1950’s 1947 Moore’s Law: The number of transistors per area doubles every years. Early 1900’s BYU CS 224 Digital Logic

The MOS Transistor A transistor acts like a switch N-type Transistor
The Transistor The MOS Transistor A transistor acts like a switch Conducts current when "ON" No current flow when "OFF" current flow gate N-type Transistor current flow gate P-type Transistor Complementary Gate (input) FET (output) GND (0) Open Vcc (3.3v) Closed Gate (input) FET (output) GND (0) Closed Vcc (3.3v) Open MOS = metal-oxide semiconductor CMOS = complementary MOS with both N and P transistors BYU CS 224 Digital Logic 14

CMOS Gates 1 Complementary pull-up / pull-down logic Pull-up Structure
The Transistor CMOS Gates 1 Complementary pull-up / pull-down logic pull-down is " ON" when pull-up is "OFF " and vise versa. Pull-up Structure (P-Type) Output Complementary Pull-down Structure (N-Type) The “C” in CMOS Even in the digital world, "EVERYTHING IS ANALOG"! BYU CS 224 Digital Logic 15

Symbols are abstractions!
Digital Logic Devices The Inverter 3.3v relative to ground. in 1 out 1 on off 1 on off Symbols are abstractions! In out 1 Truth-table lists output for all possible inputs. BYU CS 224 Digital Logic

The NOR Gate (NOT-OR) a b NOR 1 Digital Logic Devices a b NOR a b 1 1
NOR on off 1 off on a b 1 a b NOR 1 BYU CS 224 Digital Logic 17

The OR Gate How do you build an OR gate? a b OR 1
Digital Logic Devices The OR Gate How do you build an OR gate? a b 1 OR 1 a b OR 1 BYU CS 224 Digital Logic 18

The NAND Gate (NOT-AND)
Digital Logic Devices The NAND Gate (NOT-AND) b a 1 NAND on off 1 1 off on a b NAND 1 BYU CS 224 Digital Logic

The AND Gate How do you build an AND gate? a b AND 1
Digital Logic Devices The AND Gate How do you build an AND gate? AND b a AND a b a b AND 1 BYU CS 224 Digital Logic 20

Drivers Why can’t complementary logic connect to a bus? Bus
Digital Logic Devices Drivers Why can’t complementary logic connect to a bus? Bus A 0 and a 1 on the bus would let the magic smoke out! Solution: Tri-state driver: All OFF  1 Any ON  0 Bus Pull-up +3.3v Input Output Select BYU CS 224 Digital Logic 21

Digital Logic Devices Quiz 2.2 Draw a logic circuit for a 3 input NAND gate (using N for N-type transistor and P for P-type transistor). b a 1 NAND BYU CS 224 Digital Logic

Gates, Truth Tables, and Equations
BYU CS 224 Digital Logic

Notation and Precedence
Equations Notation and Precedence Logical operator notation (in order of precedence): NOT, bar, circle, ~, ¬ AND, *, ,  OR, +,  Examples: y = NOT(s) AND a AND NOT(b) y = (~s  a  ~b) + (~s  a  b) ¬(x  y) = ¬x  ¬y BYU CS 224 Digital Logic

To distribute the bar, change the operation.
De Morgan’s Law De Morgan’s Law To distribute the bar, change the operation. NOR Symbols NAND Symbols BYU CS 224 Digital Logic 25

De Morgan’s Proof A B A + B A  B 1 1 1 1 1 De Morgan’s Law BYU CS 224
1 1 1 1 1 BYU CS 224 Digital Logic

You Should Know How to Translate
Translations You Should Know How to Translate These are three different ways of representing logical information Logic Equations You can convert any one of them to any other Logic Gates Truth Tables BYU CS 224 Digital Logic

Translations Example 1 out s a b s a b out BYU CS 224 Digital Logic

Translations Example 2 A B AB (NOT(A) AND B) OR (A AND NOT(B)) BYU CS 224 Digital Logic

Example 3 C = (~A × S × B) + (A × ~S × ~B) + (A × ~S × B)
Translations Example 3 A S B C C = (~A × S × B) + (A × ~S × ~B) + (A × ~S × B) + (A × S × B) BYU CS 224 Digital Logic

Manipulating Logic Expressions
Boolean Algebra Manipulating Logic Expressions Laws (basic identities) of Boolean algebra. Law OR AND Identity x  0 = x x  1 = x One/Zero x  1 = 1 x  0 = 0 Idempotent x  x = x x  x = x Inverse x  ¬x = 1 x  ¬x = 0 Commutative x  y = y  x x  y = y  x Associative (x  y)  z = x  (y  z) (x  y)  z = x  (y  z) Distributive x  (y  z) = (x  y)  (x  z) x  (y  z) = (x  y)  (x  z) DeMorgan’s ¬(x  y) = ¬x  ¬y ¬(x  y) = ¬x  ¬y BYU CS 224 Digital Logic

Quiz Quiz 2.3 What is the logical equation and truth table for the following circuit? BYU CS 224 Digital Logic 32

FSM Lab 2: FSM Preview Output Input BYU CS 224 Digital Logic

Combinational Logic Devices

Circuits Decoders Decode the input and signify its value by raising just one of its outputs. 2-to-4 Decoder A B W X Y Z DECODER Symbol W X Y Z A B 1 if A,B = 00 1 if A,B = 01 A B W X Y Z 0 0 0 1 1 0 1 1 1 if A,B = 10 1 if A,B = 11 BYU CS 224 Digital Logic

Circuits Multiplexors Connect one of its inputs to its output according to select signals Useful for selecting one from a collection of data inputs. Usually has 2n inputs and n select lines. A B S C 1 MULTIPLEXOR Symbol A B S C A B S C 0 X 1 X X X BYU CS 224 Digital Logic

Circuits Adders At each digit position add together the 2 operands and the carry-in b3 a3 b2 a2 b1 a1 b0 a0 c 0110 +0101 1011 Full Adder Full Adder Full Adder Full Adder ‘0’ c3 c2 c1 c0 s3 s2 s1 s0 Just like longhand addition except it’s in binary... BYU CS 224 Digital Logic

Full Adder Module Design
Circuits Full Adder Module Design a b c cyout sum BYU CS 224 Digital Logic

Programmable Logic Arrays
PLAs Programmable Logic Arrays Programmable Logic Array (PLA) can be used to implement any logic function ? Inputs: Outputs: Take truth table of any logic function Convert into equation (any truth table can be expressed as set of “and” expressions “or”ed together) PLA programmed by making/breaking wire connections BYU CS 224 Digital Logic

PLA Example Out1 = ABC + ABC + ABC Out2 = ABC + ABC + ABC
PLAs PLA Example Out1 = ABC + ABC + ABC Out2 = ABC + ABC + ABC Out3 = ABC + ABC Inputs Outputs ? A B C Out1 Out2 Out3 A B C Out1 Out2 Out3 BYU CS 224 Digital Logic

Quiz 2.4 Implement a half adder using a PLA
PLAs Quiz 2.4 Implement a half adder using a PLA sum = abc + abc + abc + abc = a  b  c ? sum ? ? ? a ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? c ? ? ? ? ? ? ? ? BYU CS 224 Digital Logic

Logical Completeness Logical Completeness What is the minimum set of gate types needed to implement any logic function? AND gate, OR gate, Inverter DeMorgan’s Theorem AND gate, INVERTER OR can be replaced by an AND and three Inverters DeMorgan’s Theorem OR gate, INVERTER AND can be replaced by an OR and three Iinverters BYU CS 224 Digital Logic 42 Paul Roper 42

Logical Completeness NAND INVERTER AND OR Logical Completeness
NAND (by itself) is logically complete if you can implement an INVERTER, AND, and OR gate using only NAND gates. NAND INVERTER AND OR BYU CS 224 Digital Logic

Sequential Logic

Storage Elements Everything so far has been combinational logic
Sequential Logic Storage Elements Everything so far has been combinational logic the output is strictly a function of the current inputs Computing systems need storage elements for holding previously computed values for saving state Two types of locks: 30 15 5 10 20 25 Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3). 4 1 8 Combinational – Success depends only on the values, not the order in which they are set. BYU CS 224 Digital Logic 45

Bi-Stability = Key to Memory
Sequential Logic Bi-Stability = Key to Memory When there are 2 stable states - a bi-stable circuit RS Latch 1 This is a stable state – it will sit like this forever 1 This is also a stable state – it will sit like this forever 1 q s r 1 q s r BYU CS 224 Digital Logic 46

RS Latch – Bi-Stable Circuit
Sequential Logic RS Latch – Bi-Stable Circuit q s r This is a stable state – it will sit like this forever 1 q s r 1 This is also a stable state – it will sit like this forever 1 1 1 1 1 BYU CS 224 Digital Logic

Symbols are abstractions!
Latch Gated D Latch Output q gets value from input d only when we is high we stands for write enable, think of it as a load signal s r q d we WE D Q D-Latch LATCH Symbol Symbols are abstractions! BYU CS 224 Digital Logic

Register A computer register is a place to store a collection of bits
Latch Register A computer register is a place to store a collection of bits Very fast memory Numbered right to left (LSB on the right) d3 d2 d1 d0 we d D-Latch D-Latch D-Latch D-Latch we Register q REGISTER Symbol q3 q2 q1 q0 BYU CS 224 Digital Logic

Memory A collection of addressable locations
Address selects which location to read from or write to A memory with n address wires has 2n locations. The number of data wires in equal the number of data wires out. Memory is changed with we is asserted. q always reflects the contents stored at the addressed memory location. Memory can be viewed as a large collection of slower registers. Memory address q n we d m BYU CS 224 Digital Logic

Building a Memory From Latches
writeEnable d input q0 2-to-4 Decoder 00 we Register q1 01 we Register q output q2 10 we Register q3 11 we Register a1 a0 MEMORY Symbol Memory address q n we d m This is a functional view. The key parts are: address decoder memory cells (registers) output selector (mux) address n = 2 BYU CS 224 Digital Logic

A 12-Bit Memory 4 words, each 3 bits wide Memory Word line “00”
Only one word line is high at any given time. Word line “10” Word line “11” Latch BYU CS 224 Digital Logic

Reading a 12-Bit Memory Each column forms a sort of multiplexor Memory
Only one of the AND gates in the column will be enabled. Thus, they allow one row out of 4 to be selected for reading. BYU CS 224 Digital Logic

Writing a 12-Bit Memory 4 words, each 3 bits wide Memory
Write line “00” Write line “01” Write enable signal and write enable AND gates Write line “10” Write line “11” Depending on state of we signal, zero or one write lines will be high at any given time. Latch BYU CS 224 Digital Logic

Quiz 2.5 1. What is a bi-stable circuit?
2. With a RS NAND latch, why can’t R and S be low at the same time? 3. How is Q set with the following latch? BYU CS 224 Digital Logic 55

Finite State Machine

Computing Devices Alan Turing The Turing Machine
In 1936 he proposed a way to define the term “computable” The Turing Machine Basic abstract symbol-manipulating devices which can be adapted to simulate the logic of any computer algorithm. Anything that can be computed, can be computed by a TM… The TM is not a real machine, but an abstract machine BYU CS 224 Digital Logic

Turing Machine Details
BYU CS 224 Digital Logic Paul Roper

Turing Machine Example
Start State (State Register) “Action Table” Step State Tape 1 S1 …11000… Old Read Write New State Sym Sym Move State S1 1  0 R S2 S2 1  1 R S2 S2 0  0 R S3 S3 0  1 L S4 S3 1  1 R S3 S4 1  1 L S4 S4 0  0 L S5 S5 1  1 L S5 S5 0  1 R S1 2 S2 …01000… 3 S2 …01000… 4 S3 …01000… 5 S4 …01010… 6 S5 …01010… 7 S5 …01010… 8 S1 …11010… 9 S2 …10010… 10 S3 …10010… 11 S3 …10010… 12 S4 …10011… 13 S4 …10011… 14 S5 …10011… 15 S1 …11011… --HALT-- Tape Read Head BYU CS 224 Digital Logic Paul Roper

Sequential State Machine
Finite State Machine Sequential State Machine Another type of sequential circuit Combines combinational logic with storage “Remembers” state, and changes output (and state) based on inputs and current state State Machine Inputs Outputs Combinational Logic Circuit Storage Elements BYU CS 224 Digital Logic

Finite State Machine State of a System The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. Examples: The state of a basketball game can be represented by the scoreboard (ie. number of points, time remaining, possession, etc.) The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board. BYU CS 224 Digital Logic

State Diagram Our lock example has four different states, labeled A-D:
Finite State Machine State Diagram 30 15 5 10 20 25 Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3). Our lock example has four different states, labeled A-D: A: The lock is not open, and no relevant operations have been performed. B: The lock is not open, and the user has completed the R-13 operation. C: The lock is not open, and the user has completed R-13, followed by L-22. D: The lock is open. Open = 0 State Diagram shows states and actions that cause a transition between states. Open = 0 Open = 1 Open = 0 BYU CS 224 Digital Logic 62

Finite State Machine Finite State Machine A description of a system with the following components: A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions Often described by a state diagram. Inputs trigger state transitions. Outputs are associated with each state (or with each transition). Frequently, a clock circuit triggers transition from one state to the next. At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external (or internal) inputs. One Cycle "1" "0" time BYU CS 224 Digital Logic 63

FSM Implementation Combinational logic
Finite State Machine FSM Implementation Combinational logic Determine outputs and next state. Storage elements Maintains state representation. State Machine Inputs Outputs Combinational Logic Circuit Storage Elements Clock BYU CS 224 Digital Logic

Asleep or Awake? What is the output of this circuit? Output
Finite State Machine Asleep or Awake? What is the output of this circuit? D E Q Q' Clk Master Slave 0 or 1 ??? Output Asleep Awake Awake Asleep We isolate current state from next state with a Master/Slave flip-flop. State move thru flip-flop on each clock cycle Master stores input value when clock is LOW Slave stores Master value when clock goes HIGH BYU CS 224 Digital Logic

Storage: Master-Slave Flipflop
Finite State Machine Storage: Master-Slave Flipflop A pair of gated D-latches isolates next state from current state. (Slave responds to Master.) Master stores input value when clock is LOW Slave stores Master value when clock goes HIGH 0 is the controllling value on a NAND Low clock is the hold for the latch High clock will set or reset depending on input (11 is set and 10 is reset) Key: Clock high: A holds in the high phase and B either sets or resets (A ignores input) Clock low: B holds in the low phase and A either sets or resets During 1st phase (clock=1), previously-computed state becomes current state and is sent to the logic circuit. (Slave) During 2nd phase (clock=0), next state, computed by logic circuit, is stored in Latch A. (Master) BYU CS 224 Digital Logic Paul Roper

Finite State Machine Storage: Master-Slave Flipflop “1” “0” time SET/RESET HOLD 0 is the controllling value on a NAND Low clock is the hold for the latch High clock will set or reset depending on input (11 is set and 10 is reset) Key: Clock high: A holds in the high phase and B either sets or resets (A ignores input) Clock low: B holds in the low phase and A either sets or resets BYU CS 224 Digital Logic Paul Roper

Finite State Machine Storage: Master-Slave Flipflop “1” “0” time HOLD SET/RESET 0 is the controllling value on a NAND Low clock is the hold for the latch High clock will set or reset depending on input (11 is set and 10 is reset) Key: Clock high: A holds in the high phase and B either sets or resets (A ignores input) Clock low: B holds in the low phase and A either sets or resets BYU CS 224 Digital Logic Paul Roper

HW 2.5 BYU CS 224 Digital Logic

Simple FSM Example Combinational Logic Finite State Machine “1” “0”
0 is the controllling value on a NAND Low clock is the hold for the latch High clock will set or reset depending on input (11 is set and 10 is reset) Key: Clock high: A holds in the high phase and B either sets or resets (A ignores input) Clock low: B holds in the low phase and A either sets or resets “1” “0” time BYU CS 224 Digital Logic 70 Paul Roper 70

Simple FSM Example (Lab 2)
Finite State Machine Simple FSM Example (Lab 2) Combinational Logic 0 is the controlling value on a NAND Low clock is the hold for the latch High clock will set or reset depending on input (11 is set and 10 is reset) Key: Clock high: A holds in the high phase and B either sets or resets (A ignores input) Clock low: B holds in the low phase and A either sets or resets Sequential Logic BYU CS 224 Digital Logic 71 Paul Roper 71

Storage Elements Each master-slave flip flop stores one state bit.
Finite State Machine Storage Elements Each master-slave flip flop stores one state bit. The number of storage elements (flip flops) needed is determined by the number of states (and the representation of each state). Examples: Sequential lock 4 states – 2 bits Basketball scoreboard 7 bits for each score, 5 bits for minutes, 6 bits for seconds, 1 bit for possession arrow, 1 bit for half, … Blinking traffic sign BYU CS 224 Digital Logic

Finite State Machine Quiz 2.6 Design a State Diagram for a blinking traffic sign as follows: Switch OFF No lights Switch ON, repeat No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on Hint: How many states? 3 4 1 2 5 BYU CS 224 Digital Logic

Traffic Sign Truth Tables
Finite State Machine Traffic Sign Truth Tables Next State: S1'S0' (depend on state and input) In S1 S0 S1' S0' X 1 Switch Whenever In=0, next state is 00. Outputs (depend only on state: S1S0) S1 S0 Z Y X 1 Lights 1 and 2 Lights 3 and 4 Light 5 S0' = In  ((~S0  ~S1)  (~S0  S1)) X = S0  S1 S1' = In  ((~S0  S1)  (S0  ~S1)) Y = S1 Z = (~S0  S1)  (S0  ~S1) BYU CS 224 Digital Logic 74

Traffic Sign Logic Finite State Machine
S0' = In  ((~S0  ~S1)  (~S0  S1)) S1' = In  ((~S0  S1)  (S0  ~S1)) X = S0  S1 Y = S1 Z = (~S0  S1)  (S0  ~S1) BYU CS 224 Digital Logic

Traffic Sign Truth Tables
Finite State Machine Traffic Sign Truth Tables Next State: S1'S0' (depend on state and input) In S1 S0 S1' S0' X 1 Switch Whenever In=0, next state is 00. Outputs (depend only on state: S1S0) S1 S0 Z Y X 1 Lights 1 and 2 Lights 3 and 4 Light 5 S0' = In  ((~S0  ~S1)  (~S0  S1)) X = S0  S1 S1' = In  ((~S0  S1)  (S0  ~S1)) Y = S1 Z = S0  ~S1 BYU CS 224 Digital Logic 76

Traffic Sign Logic Finite State Machine
(~S0  ~S1) (S0  ~S1) S0' = In  ((~S0  ~S1)  (~S0  S1)) (~S0  S1) S1' = In  ((~S0  S1)  (S0  ~S1)) X = S0  S1 (S0  S1) Y = S1 Z = S0  S1 X = S0  S1 Y = (~S0  S1)  (S0  ~S1) Z = (~S0  S1)  (S0  ~S1)  (S0  S1)) BYU CS 224 Digital Logic

Finite State Machine From Logic to Data Path The data path of a computer uses logic to process information. Combinational Logic Decoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data Sequential Logic State machine -- coordinate control signals and data movement Registers and latches -- storage elements BYU CS 224 Digital Logic

MSP430 Finite State Machine
STORE:CLK1:MOV,Rd Current State DECODE:NOCLK:MOV||EVSRC EVDST:CLK1:MOV,Rd|D,ROX=Rd|STORE EVSRC:CLK1:MOV,Rs|S,ROX=Rs|EVDST STORE:CLK1:MOV,Rd|ALU,RWE,RIX=Rd|FETCH ... ALU,RWE,RIX=Rd Action FETCH Next State BYU CS 224 Digital Logic

BYU CS 224 Digital Logic Paul Roper

S02 - Digital Logic Required: PM: Ch 2, pgs 5-25

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S02 - Digital Logic Required: PM: Ch 2, pgs 5-25

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