Figure 7–1 Two versions of SET-RESET (S-R) latches

Name: Figure 7–1 Two versions of SET-RESET (S-R) latches
Uploaded: 2017-11-03T00:33:12+00:00
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Description: Figure 7–1 Two versions of SET-RESET (S-R) latches

Figure 7–1 Two versions of SET-RESET (S-R) latches
Figure 7– Two versions of SET-RESET (S-R) latches. Open file F07-01 and verify the operation of both latches. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–2 Negative-OR equivalent of the NAND gate latch in Figure 9–1(b).
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7– The three modes of basic latch operation (SET, RESET, no-change) and the invalid condition. Figure 7– The three modes of basic latch operation (SET, RESET, no-change) and the invalid condition. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–4 Logic symbols for the S-R and latch.

Figure 7–5 Thomas L. Floyd Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–6 The latch used to eliminate switch contact bounce.

Figure 7–7 The 74LS279 quad latch.

Figure 7–8 A gated S-R latch.

Figure 7–10 A gated D latch. Thomas L. Floyd Digital Fundamentals, 9e

Figure 7–12 The 74LS75 quad gated D latches.

Figure 7– Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered). Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–14 Operation of a positive edge-triggered S-R flip-flop.

Figure 7–17 Edge triggering.

Figure 7– Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7– Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–20 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.

Figure 7–22 A simplified logic diagram for a positive edge-triggered J-K flip-flop.

Figure 7–23 Transitions illustrating the toggle operation when J = 1 and K = 1.

Figure 7–26 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

Figure 7–27 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

Figure 7–28 Open file F07-28 to verify the operation.

Figure 7–29 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flop.

Figure 7–30 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flop.

Figure 7–32 Propagation delays, clock to output.

Figure 7–33 Propagation delays, preset input to output and clear input to output.

Figure 7–34 Set-up time (ts)
Figure 7– Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7– Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–36 Example of flip-flops used in a basic register for parallel data storage.

Figure 7–37 The J-K flip-flop as a divide-by-2 device
Figure 7– The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7– Example of two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–41 Flip-flops used to generate a binary count sequence
Figure 7– Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–44 A simple one-shot circuit.

Figure 7–45 Basic one-shot logic symbols
Figure 7– Basic one-shot logic symbols. CX and RX stand for external components. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–46 Nonretriggerable one-shot action.

Figure 7–47 Retriggerable one-shot action.

Figure 7–48 Logic symbols for the 74121 nonretriggerable one-shot.

Figure 7–49 Three ways to set the pulse width of a 74121.

Figure 7–50 Logic symbol for the 74LS122 retriggerable one-shot.

Figure 7–52 A sequential timing circuit using three 74LS122 one-shots.

Figure 7–53 Internal functional diagram of a 555 timer (pin numbers are in parenthesis).

Figure 7–54 The 555 timer connected as a one-shot.

Figure 7–55 One-shot operation of the 555 timer.

Figure 7–56 The 555 timer connected as an astable multivibrator (oscillator).

Figure 7–57 Operation of the 555 timer in the astable mode.

Figure 7–58 Frequency of oscillation as a function of C1 and R1 + 2R2
Figure 7– Frequency of oscillation as a function of C1 and R1 + 2R2. The sloped lines are values of R1 + 2R2. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7– The addition of diode D1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R1 < R2. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–60 Open file F07-60 to verify operation.

Figure 7–61 Two-phase clock generator with ideal waveforms
Figure 7– Two-phase clock generator with ideal waveforms. Open file F07-61 and verify the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–62 Oscilloscope displays for the circuit in Figure 7–61.

Figure 7– Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F07-63 and verify the operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 7–64 Traffic light control system block diagram.

Figure 7–65 Block diagram of the timing circuits.

Figure 7–66 The timing circuits.

Figure 7–1 Two versions of SET-RESET (S-R) latches

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Figure 7–1 Two versions of SET-RESET (S-R) latches

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