1. Chapter 10 Flip-Flops and Registers Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

2. S-R Flip-Flop Cross-coupling scheme Asynchronous Cross NOR –See Figure 10-1 –Set and Reset inputs –Function Table - See Table 10-1 Cross NAND –See Figure 10-2 –Function Table - See Table 10-2 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

3. Figure 10-1 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

4. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

5. Figure 10-2 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

6. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

7. S-R Flip-Flop Both true and complemented Q outputs Symbols - See Figure 10-3 Timing Analysis –See Example 10-1 S-R Flip-Flop Application –Strobe Gates –See Figure 10-7 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

8. Figure 10-3 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

9. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

10. Figure 10-7 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

11. Gated S-R Flip-Flop Synchronous - operates sequentially See Figure 10-8 Function Table and symbol –See Figure 10-9 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

12. Figure 10-8 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

13. Figure 10-9 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

14. Gated D Flip-Flop Data flip-flop Inverter added to S-R flip-flop Single input for both Set and Reset See Figure 10-12 Output waveform - See Example 10-4 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

15. Figure 10-12 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

16. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

17. D-Latch: 7475 IC; VHDL Description 7475 –four transparent D latches –bistable latch –See Figure 10-14 logic symbol pin configuration –Function Table - See Table 10-3 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

18. Figure 10-14 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

19. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

20. D-Latch: 7475 IC; VHDL Description VHDL description of a D-Latch –implemented using a graphic design file –implemented using VHDL –see example 10-6 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

21. D Flip-Flop: 7474 IC; VHDL Description 7474 –positive edge-triggered device transitions of output occur at the edge of input trigger pulse clock signal usually used –See Figure 10-20 logic symbol pin configuration Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

22. Figure 10-20 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

23. D Flip-Flop: 7474 IC; VHDL Description –positive edge-detection circuit See Figure 10-21 –synchronous inputs D (Data) C p (Clock) –asynchronous inputs S D (Set) R D (Reset) Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

24. Figure 10-21 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

25. D Flip-Flop: 7474 IC; VHDL Description –Function Table See Table 10-4 –Setup Time time D must be stable before transition of C p Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

26. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

27. D Flip-Flop: 7474 IC; VHDL Description VHDL description of a D flip-flop –implemented using a graphic design file –implemented using VHDL –see examples 10-9 and 10-10 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

28. Master-Slave J-K Flip-Flop Toggle mode –switch to opposite state at active clock edge Master-Slave –master receives data while input trigger is HIGH –slave receives data from master and outputs it when clock goes LOW Function Table - See Table 10-5 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

29. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

30. Master-Slave J-K Flip-Flop See Figure 10-31 –equivalent circuit –logic symbol Digital State Pulse-Triggered (Level-Triggered) –input data read during entire time clock pulse is at a HIGH level –ones catching Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

31. Figure 10-31 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

32. Edge-Triggered J-K Flip-Flop With VHDL Model Accepts data only on the J and K inputs at the active clock edge See Figure 10-37 Function Table - See Figure 10-38 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

33. Figure 10-37 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

34. Figure 10-38 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

35. Edge-Triggered J-K Flip-Flop With VHDL Model VHDL description of an edge triggered J-K flip-flop –using the CASE statement instead of multiple IF-THEN-ELSE statements –using graphic design or VHDL methods –see example 10-14 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

36. Integrated Circuit J-K Flip-Flop 7476 - master-slave 74LS76 - negative edge-triggered –See Figure 10-44 logic symbol pin configuration –Function Table see Table 10-6 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

37. Figure 10-44 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

38. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

39. Integrated Circuit J-K Flip-Flop –To form a D flip-flop add an inverter See Figure 10-51 –To form a toggle flip-flop tie inputs to HIGH See Figure 10-52 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

40. Figure 10-51 Figure 10-52 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

41. Using an Octal D Flip-Flop in a Microcontroller Application Octal ICs - eight on a chip 8-bit register 74HCT273 –See Figure 10-56 - logic diagram –See Figure 10-57 –storage Register Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

42. Figure 10-56 Figure 10-57 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

43. Using Altera’s LPM Flip-Flop General purpose FF called LPM_FF in LPM subdirectory called \mega_lpm Parameters are described in help screens Examples 10-20 and 10-21 illustrate some basic operating features Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

44. Summary The S-R flip-flop is a single-bit data storage circuit that can be constructed using basic gates. Adding gate enable circuitry to the S-R flip- flop makes it synchronous. This means that it will operate only under the control of a clock or enable signal. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

45. Summary The D flip-flop operates similar to the S-R, except it has only a single data input, D. The 7475 is an integrated-circuit D latch. The output (Q) follows D while the enable (E) is HIGH. When E goes LOW, Q remains latched. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

46. Summary The 7474 is an integrated-circuit D flip- flop. It has two synchronous inputs, D and C p, and two asynchronous inputs, S D and R D. Q changes to the level of D at the positive edge of C p. Q responds immediately to the asynchronous inputs regardless of the synchronous operations. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

47. Summary The J-K flip-flop differs from the S-R flip- flop because it can also perform a toggle operation. Toggling means that Q flips to its opposite state. The master-slave J-K slip-flop consists of two latches: a master that receives data while the clock trigger is HIGH, and a slave that receives data from the master and outputs it to Q when the clock goes LOW. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

48. Summary The 74LS76 is an edge-triggered J-K flip- flop IC. It has synchronous and asynchronous inputs. The 7476 is similar, except it is a pulse-triggered master-slave type. The 74HCT273 is an example of an octal D flip-flop. It has eight D flip-flops in a single IC package, making it ideal for microprocessor applications. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

49. Summary D latches, D flip-flops and J-K flip-flops can be described in VHDL and implemented in CPLDs. The Quartus II software provides a general purpose flip-flop in their LPM subdirectory that can be used to implement multi-bit D and toggle flip flops. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version