1. CPU Design

2. CS252/Culler Lec 1.2 1/22/02 Levels of Representation (61C Review) High Level Language Program Assembly Language Program Machine Language Program Control Signal Specification Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw$15,0($2) lw$16,4($2) sw$16,0($2) sw$15,4($2) 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 °°°° ALUOP[0:3] <= InstReg[9:11] & MASK

3. CS252/Culler Lec 1.3 1/22/02 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction

4. 4 Edge triggered D Flip-Flop Clk D Q Output changes only on the rising edge of the clock

5. CS252/Culler Lec 1.5 1/22/02 What’s a Clock Cycle? Old days: 10 levels of gates Today: determined by numerous time-of- flight issues + gate delays –clock propagation, wire lengths, drivers Latch or register combinational logic

6. In-Out control

7. Instruction 00

8. ? ??? 00 IR ??? ALU Ctrl +1 PC Out In Beginning, Program & Data in Memory Reset counter, the Machine in a random state …. MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000

9. 0 901 00 ??? ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000 Instruction Fetch (1)... PC  MAR, Read IR

10. 0 901 01 901 ??? ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

11. 0 901 01 901 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000 Instruction Execute... In  Accu IR AB 102

12. 12 JNext instruction: 01

13. 13 0101 310 01 901 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000 Instruction Fetch (1)... PC  MAR, Read IR

14. 14 0101 310 02 310 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

15. 15 1010 102 02 310 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11000 Instruction Execute... IR[adr]  MAR, Accu  MDR,Write IR AB ACCU

16. 16 JNext instruction: 02

17. 17 0202 901 02 310 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11000 Instruction Fetch (1)... PC  MAR, Read IR

18. 18 0202 901 03 901 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11000 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

19. 19 0202 901 03 901 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10000 11000 Instruction Execute... In  Accu IR AB 304

20. 20 JNext instruction: 03

21. 21 0303 311 03 901 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11000 Instruction Fetch (1)... PC  MAR, Read IR

22. 22 0303 311 04 311 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11000 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

23. 23 1 304 04 311 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 IR AB ACCU Instruction Execute... IR[adr]  MAR, Accu  MDR,Write

24. 24 JNext instruction: 04

25. 25 0404 210 04 311 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (1)... PC  MAR, Read IR

26. 26 0404 210 05 210 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

27. 27 1010 102 05 210 304 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Execute (1)... IR[adress]  MAR, Read IR AB ACCU

28. 28 1010 102 05 210 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Execute (2)... ACCU - MDR  ACCU IR AB ACCU 304

29. 29 JNext instruction: 05

30. 30 0505 808 05 210 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (1)... PC  MAR, Read IR

31. 31 0505 808 06 808 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

32. 32 0505 808 08 808 102 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Execute... (acc ≥ 0  IR[adress]  PC) IR AB ACCU

33. 33 JNext instruction: 08

34. 34 0808 902 08 808 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (1)... PC  MAR, Read IR

35. 35 0808 902 09 902 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

36. 36 0808 902 09 902 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Execute... ACCU  OUT IR AB ACCU 202

37. 37 JNext instruction: 09

38. 38 0909 000 09 902 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (1)... PC  MAR, Read IR

39. 39 0909 000 10 000 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Fetch (2)... MDR  IR, PC  1 IR AB

40. 40 0909 000 10 000 202 ALU Ctrl +1 PC Out In MAR MDR 00901 01310 02901 03311 04210 05808 06510 07211 08902 09000 10102 11304 Instruction Execute... HLT IR AB ACCU