1. 1/1/ /e/e eindhoven university of technology Microprocessor Design Course 5Z008 Dr.ir. A.C. (Ad) Verschueren Eindhoven University of Technology Section of Information and Communication Systems

2. 1/1/ /e/e eindhoven university of technology Course day contents Microprocessor design in general – instruction set and hardware architectures – steps needed to get these – architectural styles: high speed = high complexity The tool we will use: ‘IDaSS’ – ‘Register Level’ for direct hardware design – ‘Algorithmic Level’ for complex system evaluation Introduction to assignment

3. 1/1/ /e/e eindhoven university of technology Instruction Set Architecture (ISA) Describes a processor from the user’s p.o.v. Enough information to write correct programs: – where to store data, instructions and control info ‘memory spaces’ and registers: #words, #bits, addressing, overlaps, usage – how to interact with the environment accessing I/O hardware, use of interrupts and DMA – actual instructions which can be executed – instruction sequence restrictions and side effects these are artefacts of the hardware architecture!

4. 1/1/ /e/e eindhoven university of technology Hardware architecture Describes the actual processor components – ISA ‘visible’ parts must be implemented: storage in RAM/ROM/registers basic instruction operations in logic circuits – added components to get this operational: communication channels between ISA parts instruction decode and sequence control circuits Finding highest performance/cost difficult...

5. 1/1/ /e/e eindhoven university of technology Increasing the performance/cost ratio Performance = clock speed * work done per clock – clock speed determined by logic in transfer paths between clocked storage locations: the ‘critical path’ Cost = f(amount of silicon area) – every hardware part requires area to implement – f starts linear but becomes exponential soon Two ways to increase performance/cost ratio!

6. 1/1/ /e/e eindhoven university of technology Increasing performance Increase the clock speed: – choose faster logic circuit architectures faster = more parallel = more logic gates – split logic circuits to shorten the critical path requires extra storage for intermediate results Increase the work done per clock: – perform operations (even instructions) in parallel All of these require more hardware: cost increases too

7. 1/1/ /e/e eindhoven university of technology Decreasing cost Only one option available: re-use (complex) logic in different clock cycles – requires more complex communication channels – may need extra value storage and complex control Extra logic needed: may offset the amount which is saved May need more clocks: work done per clock decreases

8. 1/1/ /e/e eindhoven university of technology Steps in the processor design process (1) 1:define the ISA (lots of cycles in here!) – 1.1:define memory spaces, registers and ‘flags’ visible to the user – 1.2:define ‘abstract’ instructions in terms of operations on elements defined in 1.1 – 1.3:assign bit patterns to ‘abstract’ instructions 1.3.1:find similarities between ‘abstract’ instructions (split in sub-operations) 1.3.2:try to encode instructions as collections of sub-operation specific bit patterns

9. 1/1/ /e/e eindhoven university of technology Steps in the processor design process (2) 2:design the hardware architecture – 2.1:create ISA-visible storage and sub- operation (combinatorial logic!) parts – 2.2:interconnect these so that all sub-operations (including instruction fetch) can be executed – 2.3:design a control structure to select and schedule the sub-operations The ‘architectural style’ influences 2.2 and 2.3 The ‘IDaSS’ tool supports cyclic development

10. 1/1/ /e/e eindhoven university of technology Architectural styles Methods to create programmable hardware (= more abstract than a processor!) vary a lot Each architecture is a combination of (sometimes non-orthogonal) design choices Design choices may be independent of ISA’s, giving recognisable ‘architectural styles’

11. 1/1/ /e/e eindhoven university of technology Style 1: datapath with FSM control A ‘Finite State Machine’ is used to select the (set of-) sub-operations to be executed in a clock cycle The ‘datapath’ can be simple: little is done in parallel Low cost, simple design, low performance

12. 1/1/ /e/e eindhoven university of technology Sub-operations execute in a single clock, placing results in a register for the next sub-operation and work in parallel: Style 2: pipelined execution write dst fetch inst fetch src do op src, op, dst dati, op, dst dato, dst PC clock +1 In principle, 1 instruction per clock! In practice, dependencies between sub-operations may require waiting of ‘stages’

13. 1/1/ /e/e eindhoven university of technology More styles: parallel execution ‘Very Large Instruction Words’ pack several normal instructions together ‘Superscalar’ processors fetch and execute multiple instructions in parallel ‘Single Instruction Multiple Data’ lets one instruction operate on more data values Multiprocessing runs programs in parallel – with several independent processors – or time-shared within one processor (‘streams’) – or even ‘space shared’ within a parallel processor

14. 1/1/ /e/e eindhoven university of technology Really weird styles: look ma, no program! Dataflow machines: directed graph networks of processing nodes Fuzzy logic: ditto, optimised to handle ‘fuzzy set’ data type Neural networks: ditto, but very simple operations and huge networks Reconfigurable computing: the hardware architecture itself can be changed by loading a bit pattern into a bunch of flip-flops