1. Chapter 2 Number conversion (BCD) 8086 microprocessor Internal registers Making of Memory address

2. Instruction Execution (MOV A, X) 8088RAM Address Bus Code MOV A, X Data Bus Data 3 Fetch Instruction Issue Address of MOV A, X Control Bus Decode Instruction Decoding MOV A, X Execute Instruction Issue Address of X

3. 8088 Processor Address Lines Data Lines Control Lines Power/GND Lines Clock (33% Duty cycle) Reset Pin held high for min. of 4 clk cycles Executes instruction at FFFF0 H Disables interrupts

4. Address & Data Bus Address Bus Size Size of Memory accessible by Processor 20 bit = 1 MByte 8088 A 0 - A 19 Address Lines Data Bus Size Chunk of Data accessible 8088 D 0 – D 7 Data Lines 8086 D 0 – D 15 Data Lines 8088 Address and Data Bus Multiplexed

6. Multipurpose/General Purpose Registers AX Accumulator 16-bit register AH and AL 8-bit Registers AX Used for Arithmetic & logical operations Used specifically for multiplication, division and adjustment instructions Holds offset address of a location in memory BX Base Index 16-bit register BH and BL 8-bit Registers Used for Arithmetic and Data operations Holds offset address of a location in memory

7. Multipurpose/General Purpose Registers CX Count 16-bit register CH and CL 8-bit Registers Used for Arithmetic and data operations Holds count value for various instructions Counts the number of characters in string operations

8. Multipurpose/General Purpose Registers DX Data 16-bit register DH and DL 8-bit Registers Used for Arithmetic and Data Operations Holds the high 16-bits of the product in multiplication operations Holds remainder for 16-bit division Holds I/O addresses

9. Base Registers Base Pointer BP 16-bit Register Points to a memory location Holds an offset or displacement from Stack Segment (SS) Register Used by subroutines to locate variables passed on stack by calling program BX Base Index 16-bit register BH and BL 8-bit Registers Used for Arithmetic and Data operations Holds offset address of a location in memory

10. Index Registers Destination Index DI 16-bit Register Addresses string destination for string instructions Holds an offset or displacement from ES register Source Index SI 16-bit Register Addresses string source for string instructions Holds an offset or displacement from DS register

11. Stack Pointer Registers Stack Pointer SP 16-bit Register Addresses Stack memory Holds an offset or displacement from SS Register Contents are combined with contents of SS Register to give address of top of stack

12. Special Registers Instruction Pointer IP 16-bit Register Points to the next instruction in the Code Segment Contents are combined with contents of Code Segment (CS) Register to give address of next instruction to be fetched Flag 16-bit Register Contents of this register are neither data nor address Individual bits in this register indicate different status information Individual bits are set (1) or cleared (0) as a result of an operation by the microprocessor

13. Special Registers Bit 0: Carry Flag Set to indicate occurrence of Carry Bit 2: Parity Flag Set to indicate even Parity Bit 4: Auxiliary Flag Set to indicate occurrence of Aux. carry Bit 6: Zero Flag Set to indicate Zero result

14. Special Registers Bit 7: Sign Flag Set to indicate a negative number Bit 8: Trap Flag Set to enable Debug mode Bit 9: Interrupt Flag Set to indicate interrupt enabled Bit 10: Direction Flag Set to 1 automatically decrements DI & SI Set to 0 automatically increments DI & SI

15. Special Registers Bit 11: Overflow Flag Set to indicate an overflow

16. Lecture 0216 DC Characteristics Input Characteristics Input current and voltage requirements Logic 0 0.8 V max ±10  A max Logic 1 2 V min ±10  A max Inputs gate connections of MOSFETs Leakage currents

17. Lecture 0217 DC Characteristics Output Characteristics Output current and voltage requirements Logic 0 0.45 V max 2.0 mA max Logic 1 2.4 V min -400  A max Reduced noise immunity 350 mV Avoid long connections Avoid too many loads Max. 10 loads without Buffering

18. How to make address.

19. CHAPTER 8

20. Lecture 0220 Bus Buffering & Latching Bus should be buffered for large systems Multiplexed Address & Data Buses should be De-multiplexed Why De-multiplexed Buses? Address on the Address Bus has to remain constant throughout a read and write cycle Read and Write Cycle? 8088/8086 read/write operation is completed in a minimum period of 4 clocks

21. Lecture 0221 Bus De-Multiplexing During T1 clock of Read/write cycle 8088 issues address AD 0 to AD 7 & A 8 to A 19 8088 activates ALE signal (Address Latch Enable)

22. Lecture 0222 373 Latch

23. Lecture 0323 Bus Buffering Address Lines A 0 – A 19 have to be buffered A 0 – A 7 & A 16 – A 19 have been buffered by 373 Logic 0 sinks 32 mA Logic 1 sources 5.2 mA A 8 – A 15 have to be buffered 74LS244 Octal Buffer used for Buffering

24. De-multiplexed Bus 8088 AD 0 – AD 7 373 Latch 373 A 0 – A 7 A 8 – A 15 A 16 – A 19 ALE LE GND OE* D 0 – D 7

25. Lecture 0325 Clock Circuitry Clock Generator 8284 Clock Signals Reset Synchronization READY Synchronization TTL-level peripheral clock

26. Lecture 0426 Clock Generator 8284

27. Lecture 0427 Processor RESET RESET pin needs to remain high for min. of 4 clocks and must not go low for at least 50  s

28. Lecture 0428 Bus Timing Memory & I/O is slow Rate of data transfer depends on access time of Memory & I/O Processor Read/Write cycles have to be extended to allow transfer from slow devices Basic Bus Operation Address, Data and Control Buses are involved in reading and writing of data Address, Data and Control Bus operations are carried out in a sequence

29. Lecture 0429 Bus Timing 8086/8088 use the Memory/IO in periods called Bus Cycles Each Bus Cycle equals 4 system clocking periods (T states) Pentium has 2 T state Bus cycle At 5 MHz, one Bus cycle is completed at 0.8  sec or 800 nsec Processor can read/write at a max. rate of 1.25 million times a sec.

30. Lecture 0430 Bus Timing With internal queue processor can execute 2.5 million instructions per sec. [MIPS] in bursts Pentium operates at much higher rates due to higher clock rates, shorter Bus cycle and internal queuing

31. Lecture 0431 Bus Timing T1 Clock Address of the Memory/IO is issued via the Address/Data Multiplexed Bus Following Signals are also issued ALE Address Latch Enable signal DT/R* Data Transmit/Receive signal IO/M*IO/Memory signal

32. Lecture 0432 Bus Timing T2 & T3 Clocks RD* or WR* Read or Write Signal is issued Incase of Write the Data to be written also appears on the Data Bus DEN* Data Bus Enable signal is issued READY signal is sampled at the end of T2 If READY is low T3 becomes a Wait State T W READY is again sampled in the middle of Wait State If the Bus Cycle is Read Cycle, Data Bus is sampled at the end of T3

33. Lecture 0433 Bus Timings T4 Clock All Bus signals are deactivated in preparation for the next Bus Cycle During a Read Cycle the processor continues to sample the Data Bus during T4 cycle During a Write Cycle the trailing edge of the Write signal transfers the data to Memory or IO

34. Minimum Vs. Maximum Mode 8088/8086 has two Modes of operation Minimum Mode Maximum Mode Minimum Mode Operation similar to 8085 (8 bit processor) MN/MX* pin connected to +5 V 8-bit peripherals can be used with 8088/8086

35. Minimum Vs. Maximum Mode Maximum Mode Enhanced Operation used whenever a coprocessor is used with 8088/8086 MN/MX* pin connected to GND 8288 Bus Controller required to generate extra signals

36. Summary

37. Memory Interface Memory Pin Connections Address Pins Data Pins Control Pins Selection Pins

38. Memory Interface Address Pins Number of locations in memory determine the number of Address Pins 4 K = 12 lines 1 M = 20 lines

39. Memory Interface Data Pins Width of memory determines the number of Data Pins 8 bit width = 8 lines 1 bit width = 1 line

40. Memory Interface ROM Control Pins OE* or G* allows data to flow out RAM Control Pins WE* allows data to be written OE*allows data to be read Can have a single R/W* pin

41. Memory Interface Selection Pins CE* or CS* allows the RAM/ROM chip to be selected Sometimes there are more than one CS* signal

42. ROM Read Only ROM Permanently stores program/data Does not allow write (read Only)

43. 2764 (8 KB) EPROM

44. Address Decoding Processors have very large address space Pentium 4 has a 64 GB memory space Entire memory space is not used Processor memory space is used for specific purpose Operating System Program Code Data Interrupt Vector Table

45. Address Decoding RAM, ROM and I/O devices are mapped in the processor memory space More memory can be added in the vacant memory space

46. Memory Mapping Least significant lines of the processor address bus always connected to the address lines of the Memory chip (A 0 – A 18 ) Most significant line(s) of the processor address bus always used for mapping memory chip in the address space and connected to the chip select (A 19 ) First 512 KB Ram chip selected when A 19 = 0 Second 512 KB Ram chip selected when A 19 = 1

47. Memory Mapping

48. 256 KB RAM chip (A 0 – A 17 ) Four 256 KB RAM chips should be connected to completely map the 1 MB processor memory space Address Lines A 18 & A 19 used for chip selection

49. Gate Decoder 1 st 256 KB RAM chip selected when A 19 = 0 & A 18 = 0 A two input OR gate 2 nd 256 KB RAM chip selected when A 19 = 0 & A 18 = 1 A two input OR gate with A 18 input inverted 3 rd 256 KB RAM chip selected when A 19 = 1 & A 18 = 0 A two input OR gate with A 19 input inverted 4 th 256 KB RAM chip selected when A 19 = 1 & A 18 = 1 A two input NAND gate

50. Lecture 0850 Designing Address Decoders Flexible Design can be easily modified Allow for future expansion Should introduce minimum gate delay Low chip count

51. Lecture 0851 Address Decoding Full Address Decoding Entire address space is fully decoded More decoding circuitry is required Partial Address Decoding Address space is not fully decoded Less decoding circuitry is required Address clashes occur Block Address Decoding Memory space divided into blocks of equal sizes

52. Lecture 0852 Address Decoding example

53. Lecture 0853 Address Decoding example

54. Lecture 0854 Address Decoding example

55. Lecture 0855 Address Decoding example

56. Lecture 0856 Types of Address Decoders Logic Gate Decoders Simple Irregular structure No future expansion allowed M x N Decoders Regular structure Future expansion allowed Divides address space into equal sized blocks

57. Lecture 0857 Types of Address Decoders ROM based Decoders Very flexible New decoding scheme implemented by reprogramming the ROM PLDs based Decoders Very flexible have replaced PROM based Decoders

58. Lecture 0958 Block-Address Decoding example

59. Lecture 0959 Address Decoding Example Map the memory chips in contiguous memory locations starting from address 0000 H with minimal empty slots 2K ROM1, 4K RAM1, 1K RAM2, 2K RAM3 How should it be done? Start by sketching an Address Decoding Table

60. Lecture 0960 Address Decoding Example A 15 – A 12 A 11 – A 8 A 7 – A 4 A 3 – A 0 ROM12K00000XXXXXXX RAM14K0001XXXX RAM21K001000XXXXXX RAM32K00101XXXXXXX

61. Lecture 1061 Types of Address Decoders Logic Gate Decoders Simple Irregular structure No future expansion allowed High chip count High decoding speed

62. Lecture 1062 Types of Address Decoders M x N Decoders Regular structure Future expansion allowed Divides address space into equal sized blocks Low chip count

63. Lecture 1063 Types of Address Decoders ROM based Decoders Very flexible New decoding scheme implemented by reprogramming the ROM PLDs based Decoders Very flexible have replaced PROM based Decoders

64. 8088 Processor Address Lines Data Lines Control Lines Power/GND Lines Clock (33% Duty cycle) Reset Pin held high for min. of 4 clk cycles Executes instruction at FFFF0 H Disables interrupts

65. 8288 bus controller

67. 8155 chip