1. EE314 Microprocessor Systems
Chapter 5
Interrupt processing
Objectives:
The difference between hardware and software interrupts
The difference between maskable and nonmaskable interrupts
Interrupt processing procedures
The vector address table
Multiple interrupts and interrupt priorities
Special function interrupts
The general requirement of all interrupt handlers
Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos

2. 5.2 Hardware and Software Interrupts
The nonmaskable interrupt is generated by en external device, trough a rising edge on the NMI pin.
Cannot be ignored by the microprocessor.
Generates a Type 2 interrupt (address 0008H in the Interrupt vector table)
The maskable interrupts (0…FFH) can be generated by:
an external device, trough a high logic level on the INTR pin (the external device has to specify the interrupt number).
Hardware
interrupts
(IF (interrupt flag) in FLAGS register enables or disables (masks) the P to accept maskable interrupts.)
microprocessor itself (i.e. when trying to divide by 0), (the interrupt number is hardware defined).
Software interrupts (exceptions) using the INT instruction (followed by the interrupt number (type)).
Interrupt priority
Divide-error Highest
INT, INTO
NMI
INTR
Single-step Lowest

3. 5.3 The Interrupt Vector Table
(or Interrupt Pointer Table)
The memory block from address to 003FF. There are 1024 bytes, each of the 256 maskable interrupts uses four bytes to store the address where the corresponding ISR (Interrupt Service Routine) begins. The ISR address for interrupt number xx is stored beginning at address xx*4, in form CS:IP. From low to high address, the bytes are stored in the order: IP low, IP high, CS low and CS high (byte swapping).
Consequences:
After RESET the P cannot begin running from physical address
The first instruction is fetched at address FFFF0H.
Before using an interrupt, its corresponding ISR address has to be stored in the interrupt vector table.
ISRs are handled as FAR routines (both CS and IP specified).
Vectors 0 to 18 are predefined, 19 to 31 are reserved by Intel, 32 to 255 are unassigned (free to use):

4. 5.4 The Interrupt Processing Sequence
Hardware INTR
Internal HW Int.
Software Interrupts no
yes
Interrupt not accepted
IF=1
IF=1
yes no
Inform external devices that an interrupt acknowledge cycle began
first INTA cycle
( INTA pin = low)
(Pentium -
M/IO,D/C,W/R,ADS = 0)
Interrupt not accepted
The interrupt type is the operand
NMI
External devices requesting an interrupt transmits trough data bus the interrupt type
The interrupt type is predefined
second INTA cycle
read interrupt type on Data Bus
Save processor information on stack:
- FLAGS register
- Return address = CS:IP
Fetch the address of the ISR:
- CS:IP from Interrupt Vector Table
at address 4*(interrupt type)
Clear IF and TF (no further
maskable interrupts allowed)
ISR execution

5. Return to interrupted program
5.5 Multiple Interrupts
ISR execution
(non NMI)
NMI ISR execution
IRET no
yes
NMI
Execution of all instructions no
NMI
Execution of 1 instruction
The interrupt type is predefined
Load processor information from stack:
- Return address = CS:IP
- FLAGS register
Return to interrupted program
IRET
Load processor information from stack:
- Return address = CS:IP
- FLAGS register
Save processor information on stack:
- FLAGS register
- Return address = CS:IP
Clear IF and TF (no further
maskable interrupts allowed)
Fetch the address of the NMI ISR

6. 5.6 Special Interrupts generates a type 0 interrupt.
0400:1100 B MOV BL,0
0400:1102 F6 F3 DIV BL
0400:1104 ….
Divide Error: type 0, hardware generated by the P when quotient doesn’t fit in destination (division by 0)
return address
Single step: type 1, hardware generated by the P (if TF=1) after each instruction. After pushing flags onto stack, TF is cleared (IF also), so ISR itself is not interrupted. Returning after ISR, the flags are restored, another interrupt is generated after next instruction.
A program example to set or reset the TF:
PUSHF
POP AX
OR AX,100H
PUSH AX
POPF
moves FLAGS to AX
PUSHF
POP AX
OR AX,100H
PUSH AX
POPF
updates TF
moves AX to FLAGS
Replaced by INT 3 code (CCH)
by setting a breakpoint.
NMI: type 2, hardware generated by an external device on emergent events (i.e. power fail). Rising edge active.
0400: C CMP AL,0
0400: JNZ XYZ
0400:1104 EE OUT DX,AL
0040:1105 FE C0 XYZ: INC AL
Breakpoint: type 3, software generated by a single-byte instruction, INT 3.
Overflow: type 4, generated by INTO instruction if OF=1.
Interrupt request has to stay active until acknowledged:
External maskable interrups: type via INTR pin
P generates two pulses on INTA pin. During the second pulse, the external device has to put on data bus (D0…D7) the interrupt type.

7. 5.6 Special Interrupts
Interrupts may occur in unexpected moments during main program execution (i.e. between setting of a flag as result of an arithmetical instruction and the subsequent conditional jump hanging on the flag value). After returning from ISR, the main program has to continue undisturbed by changes made in P’s internal state (environment or context): flags, registers.
An ISR can perform multiple functions hanging on the value of an input parameter (i.e. the value in the AH register).
Before occurrence of the interrupt (usualy a software one) the value of the parameter is prepared.
The corresponding ISR tests the parameter and perform the action required by its value.
The interrupt acknowledge mechanism saves FLAGS and return address, but no register content.
The Interrupt Service Routine (ISR) is responsible for saving all the used register’s value on stack (PUSH), and to recover it (POP) before returning.
MYISR: PUSHA …
POPA
IRET
Usually, all registers are saved (PUSHA) and recovered (POPA)

8. 5.6 Special Interrupts
A simple circuit able to place an 8-bit interrupt number (type) onto data bus
second active pulse of INTA
first active pulse of INTA
P is reading the byte on AD7…AD0
INTR can deactivate after activation of INTA
Interrupt
request
...
INTR
AD7 .
AD0
INTA
INTR
INTA
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0 1
+5V
8 x 4.7K
74LS
244
(octal
buffer)
G1 G2
The octal buffer outputs are three-state
Data BUS is free for carrying data between P and other devices in system
The octal buffer controls the Data BUS.

9. 5.6 Special Interrupts A simple prioritized interrupt circuitry
P is reading the byte on AD7…AD0
INT 0D0H requested
A simple prioritized interrupt circuitry
second active pulse of INTA
first active pulse of INTA
INTA deactivates INTR
P interrupt
request
INT2
INTR
INTA
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
...
INTR
AD7 .
AD0
INTA 1
+5V
4.7K
INT2 request
74LS
374
(octal
flip-flop) OE
INT0
INT2 .
INT7
(priority encoder)
E GS
+5V
4.7K
D Q
CLR
The octal buffer outputs are three-state
Data BUS is free for carrying data between P and other devices in system
The octal buffer controls the Data BUS.

10. 5.7 Interrupt Service Routines
Simple example: one second time interval generator using a 60Hz signal on NMI
; ISR for NMI
NMITIME: DEC COUNT ;decrement 60th’s counter, (COUNT)(COUNT)-1
;(ZF)1 if (COUT)=0
JNZ EXIT ;did we go to 0?, jump only if (ZF)=0
MOV COUNT, 60 ;yes, reload the counter, (COUNT)3Ch
CALL FAR PTR ONESEC ;call ONESEC, [SP-1],[SP-2] (CS),
;[SP-3],[SP-4]EXIT,(SP)(SP)-4
;reverse action when return from ONESEC
EXIT: IRET ;(IP)[SP],[SP+1], (CS)[SP+2],[SP+3],
;(FLAGS)[SP+4],[SP+5], (SP)(SP)+6,
;reverse action to what
;happened accepting NMI
; main program slide preparing the action of NMI’s ISR
MOV COUNT, 60 ;init 60th’s counter , (COUNT)3Ch
PUSH DS ;save current DS content , [SP-1],[SP-2] (DS),(SP) (SP)-2
SUB AX, AX ;set new DS content to 0000, (AX) 0
MOV DS, AX ;(DS) 0
LEA AX, NMITIME ;load address of NMITIME ISR, (AX) NMITIME
MOV [8], AX ;store IP address in IPT, replacing regular NMI’s ISR address
;[8],[9] NMITIME
MOV AX, CS ;store CS address in IPT, (AX) (CS)=current code segment
MOV [0AH], AX ;[0Ah],[0Bh] (CS)
POP DS ;get old DS content back, (DS)  [SP],[SP+1], (SP) (SP)+2

11. 5.7 Interrupt Service Routines
Simple example: A Divide-Error Handler
If a divide error occurs, the ISR will load AX wit 101h, and DX with 0. A error message will be displayed. The error message is in DATA segment beginning at address DIVMSG and ends wit a “$” character. The DISPMSG procedure (subroutine) (not shown) displays the character string found in DATA segment until the first “$” character. ISR address has to be loaded (not shown) at address 0000 in the IPT (INT 0).
; preparing the error message in DATA segment
.DATA
DIVMSG DB ’Division by zero attempted!$’
;first character, ”D”, at address DIVMSG in DATA segment
; ISR for Divide-Error
DIVERR: PUSH SI ;save current SI content , [SP-1],[SP-2] (SI),(SP) (SP)-2
MOV AX, 101h ;load result with default, (AX) 101h
SUB DX, DX ;clear DX, (DX) 0
LEA SI, DIVMSG ;init pointer to error message, (SI) DIVMSG
;(passing parameter trough register)
CALL FAR PTR DISPMSG ;output error message, [SP-1],[SP-2] (CS),
;[SP-3],[SP-4]return address,(SP)(SP)-4
;reverse action when return from DISPMSG
POP SI ;get old SI content back, (SI)  [SP],[SP+1], (SP) (SP)+2
IRET ;(IP)[SP],[SP+1], (CS)[SP+2],[SP+3] =return address =
;(the address of the first instruction
;after the DIV generating the error)
;(FLAGS)[SP+4],[SP+5], (SP)(SP)+6,
;reverse action to what happened accepting INT 0

12. 5.7 Interrupt Service Routines
Simple example: An ISR with Multiple Functions
; ISR for INT 20H
ISR20H: CMP AH, 4 ;AH must be 0-3 only
;(?)(AH)-4, (ZF)1 if (?)=0, (CF)1 if (?)<0 (unsigned)
;(OF)1 if (?)<-128 or (?)>127,
;(PF)1 if (?) contains an even number of “1”s,
;(AF) if a transport from bit 3 to bit 4 occurred,
;(SF) if (?)<0 (signed)
JNC EXIT ;AH >3, ISR returns without any effect
CMP AH, 0 ;AH = 0 ?, (?)(AH)-0, (ZF)1 if (?)=0, ...
JZ ADDAB ;AH = 0, jump to add function
CMP AH, 1 ;AH = 1 ?, (?)(AH)-1, (ZF)1 if (?)=0, ...
JZ SUBAB ;AH = 1, jump to subtract function
CMP AH, 2 ;AH = 2 ?, (?)(AH)-4, (ZF)1 if (?)=0, ...
JZ MULAB ;AH = 2, jump to multiply function
DIVAB: DIV BL ;AH = 3, use divide function
IRET
ADDAB: ADD AL, BL ;add function
SUBAB: SUB AL, BL ;subtraction function
MULAB: MUL BL ;multiply function
; main program has to store the address of INT 20’s ISR at address 80h in IPT.