1. Introduction to Microprocessors (CS 45) Session 5 8085 Microprocessor - 2

2. AGENDA Architecture Microprocessor Communication and Bus Timings Demultiplexing Address and Data Lines

3. Architecture of 8085 Reveals the internal logic of a Microprocessor 8085 Architecture consists of following blocks: –ALU logic –Register Logic –Timing and Execution Logic –Interrupt Logic –Serial I/O Logic

4. Flag Register SZ X AC X P X C Sign Zero Carry Parity Auxiliary Carry X - Unspecified

5. Register Section General Purpose Registers A, B, C, D, E, H, and L BC, DE, and HL Special Function Registers Program Counter Stack Pointer

6. Timing and Execution Logic Instruction Register Instruction Decoder Timing and Control Unit Control Signals

7. Interrupt Logic Consists of 5 interrupts with following properties: Priority Maskable and Non Maskable Vectored and Non – Vectored INTA is an output signal

8. Serial I/O Logic Supports serial I/O using 2 lines SID – Serial Input Data SOD – Serial Output Data

9. Mp communication and Bus Timings - 1  The instruction code 0100 1111 (4FH – MOV C, A) is stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched

10. Mp Communication And Bus Timings - 2 B C D E H L SP PC Internal Data Bus ALU Instruction Decoder 4F Memory 2000 2005 Address Bus Control Logic RD 4F Data Bus 4F

11. Timing Diagram

12. Demultiplexing Address & Data Lines

13. Some Terminologies: After observing timing diagram we can say, 4FH is a one – byte instruction One external operation – fetching 4F from 2005H Entire operation needs 4 clock periods Instruction Cycle Machine Cycle T – State or Clock Period

14. What we studied in this session.. 8085 Architecture 8085 Communication and bus timings Opcode Fetch Machine Cycle Demultiplexing Address & Data Lnes

15. Probable Questions..  Explain with a neat diagram, the architecture of 8085 microprocessor  Explain the flag register of 8085.  With a neat diagram, explain how to separate multiplexed address and data lines in 8085.  Explain opcode fetch machine cycle. (Dec 06) (06)  What Signals are activated when I/O port at address ABCD H is read by 8085 ? (June 04) (10)read

16. Thank You