1. NDG-L37-41Introduction to ASIC Design1 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor*  Basic Features A Load/Store Machine, with each Instruction Cycle of 4 Machine (Clock) Cycles, 16-bit Data Bus, 12-bit Address Bus Two 16-bit Working Registers, A and B, Directly Accessible to the Programmer Memory-Mapped I/O Operations All Data Transformations are Performed in Working Registers Supports “Direct Access”, “Implicit” and “Stack” Addressing Modes Custom Defined Instructions and Functional Blocks

2. NDG-L37-41Introduction to ASIC Design2 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  Programmable Model – User Directly Accessible Registers  Invisible Registers: PC, SP, TEMP, and ST Fig-01: SIMP Programming Model

3. NDG-L37-41Introduction to ASIC Design3 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  Instruction Set and Instruction Format – All Instructions are 16-bit wide (One Memory Word) Direct Addressing Mode: 4 MSBs represent OPCODE and 12 LSBs represent Memory Address Implicit or Stack Addressing Mode -

4. NDG-L37-41Introduction to ASIC Design4 (cont’d) Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  Instruction Set and Instruction Format – Cont’d

5. NDG-L37-41Introduction to ASIC Design5 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  Instruction Set and Instruction Format – Cont’d  Memory Reference Instructions – Direct or Stack Addressing Mode (Depending on Bit-15)

6. NDG-L37-41Introduction to ASIC Design6 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  Instruction Set and Instruction Format – Cont’d  Other SIMP Core Instructions – All Implicit Mode

7. NDG-L37-41Introduction to ASIC Design7 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  SIMP Datapath Fig-02: SIMP Datapath

8. NDG-L37-41Introduction to ASIC Design8 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  SIMP Control Flow – Fetch (T0/T1), Decode (T2), Execute (T3)Execute (T3) Fig-03: SIMP Control Flow Diagram

9. NDG-L37-41Introduction to ASIC Design9 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  SIMP Instruction Execution Flowchart Fig-04: Instruction Execution Cycle

10. NDG-L37-41Introduction to ASIC Design10 Design of a Simple Customizable Microprocessor * Chapter 7 and 15, “Digital System Design and Prototyping”  SIMP – A Simple Customizable Microprocessor* - Cont’d  SIMP Implementation – Datapath + Control Unit Datapath consists of all registers + interconnect structures (such as Muxes) and ALU etc. Control Unit provides proper timing, sequencing, and synchronization of micro-operations, other activation signals + control signals for external world Fig-05: Basic Partition of SIMP Design