1. Logic Process Development at Intel
PhD Fellowship Forum October 21, 2004
Logic Process Development at Intel
Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Logic Technology Development

2. Technology & Manufacturing
Intel Organization
Board of Directors
A. Grove
Executive Office
C. Barrett, P. Otellini
Enterprise Platforms
Desktop Platforms
Mobile Platforms
Intel Comm. Group
Software & Solutions
Technology & Manufacturing
Sales & Marketing
Corporate Comm.
Corporate Technology
Finance
Legal
Intel Capital

3. LTD Organization Logic Technology Development Components Research
Portland
Technology Development
Manufacturing Ramp
Advanced Research
Develop & Ramp
Manuf. Ramp
LTD Design
Technology Computer Aided Design
Sort/Test
Technology Development
Lead Product Design
Modeling & Simulations
CPU Sort and Test
Research, development, design and early manufacturing all under one group

4. LTD Charter Develop Intel's leading edge logic technologies
Ensure leadership in performance and manufacturability
Design lead high-volume microprocessor product
Ensure early product introduction
Process and product design are jointly optimized
Produce initial volumes of product shipments
Learn how to develop and manufacture new technologies
Transfer technologies to high-volume fabs using Copy Exactly! methodology
High volume manufacturing fabs come up with same performance and yield as development fab

5. Microprocessor Transistor Count

6. Feature Size Scaling

7. Transistor Gate Length Scaling

8. Logic Technology Evolution
Process Name P858 Px60 P1262 P1264 P1266 P1268
1st Production
Lithography 0.18mm 0.13mm 90nm 65nm 45nm 32nm
Gate Length 0.13mm 0.07mm 50nm 35nm 30nm 25nm
Wafer (mm) /
Manufacturing
Fabs
Development
PTD
Research CR

9. 90 nm Generation Transistor
NiSi Layer
1.2 nm SiO2 Gate Oxide
Strained Silicon
50nm

10. Polysilicon Gate Electrode
1.2 nm Gate Oxide
Polysilicon Gate Electrode
1.2 nm SiO2
Silicon Substrate
Gate oxide is less than 5 atomic layers thick

11. Intel’s Strained Silicon Technology
Selective SiGe S-D
Tensile Si3N4 Cap
PMOS
Uniaxial Compressive Strain
NMOS
Uniaxial Tensile Strain

12. Strained Silicon Technology
High
Stress
Film
SiGe
SiGe
PMOS NMOS
~30% drive current increase ~10% drive current increase

13. 90 nm Generation Interconnects
Low-k CDO
Dielectric
Copper
Interconnects

14. Low-k Dielectric
New low-k carbon doped oxide (CDO) used for interconnect dielectric
CDO provides ~20% capacitance reduction compared to SiO2
Reduced interconnect capacitance provides improved performance and lower chip power
CDO
SiN Cu

15. 90 nm Pentium® Microprocessors
Prescott CPU Dothan CPU
125 million transistors
140 million transistors

16. 90 nm Itanium® Microprocessor
Montecito CPU
1.72 billion transistors
24 MByte cache
Dual core

17. 90 nm Wafer Fabs
90 nm process now running in high volume manufacturing in three 300 mm wafer fabs:
D1C - Hillsboro, Oregon
F11X - Albuquerque, New Mexico
F24 - Leixlip, Ireland
All factories using Copy Exactly! methodology for matched yield and performance

18. Yield Improvement Trend
130nm 130nm 90nm
200mm 300mm 300mm
90 nm defect reduction rate is fastest ever

19. CPU Shipments Transitioning to 90 nm
Total CPU Shipments
Estimate
Intel 90 nm CPU shipments exceeded 130 nm CPU shipments in 3Q ’04

20. Logic Technology Evolution
Process Name P858 Px60 P1262 P1264 P1266 P1268
1st Production
Lithography 0.18mm 0.13mm 90nm 65nm 45nm 32nm
Gate Length 0.13mm 0.07mm 50nm 35nm 30nm 25nm
Wafer (mm) /

21. Intel’s Strained Silicon Technology
65 nm transistors use same basic strain technique introduced on 90 nm transistors
The strain technique is further enhanced on the 65 nm process to provide increased performance
At the 65 nm generation, strained silicon improves performance ~30% relative to non-strain S D G

22. Transistor Performance vs. Leakage
Better
Better
Improved transistors provide increased drive current (ION)
at constant leakage current (IOFF)

23. Improved Transistor Performance
90 nm transistors have continued to improve

24. Improved Transistor Performance
65 nm transistors increase drive current 10-15% with enhanced strain

25. Reduced Transistor Leakage
65 nm transistors can alternatively provide ~4x leakage reduction

26. Lithography Challenge
130nm
90nm
Feature Size
65nm

27. Lithography Challenge
Minimum feature size is scaling faster than lithography wavelength

28. Lithography Challenge
Advanced photo mask techniques help to bridge the gap

29. Alternating Phase Shift Masks
Side View
35 nm line
Chrome
Chrome 0°
180°
Glass
Glass
Silicon Substrate
Printed Lines on Si Wafer
Standard Mask
Phase Shift Mask
APSM enables patterning 35 nm lines using 193 nm wavelength light
APSM requires new mask making technology, done in-house at Intel

30. 65 nm Generation Interconnects
Cu Line
Cu Via
CDO Low-k Dielectric

31. Intel 6-T SRAM Cell Size Trend
Transistor density continues to double every 2 years

32. 0.57 mm2 6-T SRAM Cell
Ultra-small SRAM cell used in 65 nm process packs six transistors in an area of 0.57 mm2
This cell is optimized for both small area and ability to operate large SRAM arrays at low voltage

33. 70 Mbit SRAM on 65 nm Process 0.57 mm2 cell size 110 mm2 chip size
>0.5 billion transistors
Incorporates all process features needed for 65 nm logic products
Used to debug and demonstrate process yield, performance and reliability

34. 65 nm Wafer Fabs Process development site Manufacturing sites
D1D, Oregon
Intel's largest individual clean room
176,000 sq ft (roughly the size of 3.5 football fields)
Manufacturing sites
F12, Arizona
F24, Ireland

35. Scaling Gets Tougher at Smaller Dimensions

36. Scaling Gets Tougher at Smaller Dimensions
Intel continues to develop and implement new materials and structures to meet the challenge

37. Scaling Gets Tougher at Smaller Dimensions
Intel continues to develop and implement new materials and structures to meet the challenge

38. For further information on Intel's silicon technology,
please visit the Silicon Showcase at: