1. Sample-and-Hold (S/H) Basics
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Sample-and-Hold (S/H) Basics

2. ZOH vs. Track-and-Hold (T/H)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
ZOH vs. Track-and-Hold (T/H)
Zero acquisition time
Infinite bandwidth
Not realistic
T/2 acquisition time
Finite bandwidth
Practical

3. A Simple T/H (Top-Plate Sampling)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
A Simple T/H (Top-Plate Sampling)
MOS technology is naturally suitable for implementing T/H
The lowpass SC network determines the tracking bandwidth
Non-idealities: signal-dependent Ron, charge injection, aperture, etc.

4. Tracking Bandwidth (TBW)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Tracking Bandwidth (TBW)
Tracking bandwidth determines how promptly Vo can follow Vi
Typically TBW is many times greater than the max signal bandwidth
What’s wrong with the concept of “linear filtering” if Ron is constant?

5. Dispersion Magnitude response Non-uniform phase delay
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Dispersion
Magnitude response
Non-uniform phase delay
Non-uniform group delay

6. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Dispersion
Waveform is not very sensitive to the lowpass magnitude response as long as the signal bandwidth is on the order of TBW
Waveform distortion is mainly due to non-uniform phase and group delays

7. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Signal-Dependent Ron
Signal-dependent Ron → signal-dependent TBW → extra waveform distortion
Neither signal-dependent Ron nor dispersion is of concern if TBW is
sufficiently large (>> fin, depending on the target accuracy)

8. Ideal T/H Sufficient tracking bandwidth → negligible tracking error
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Ideal T/H
Sufficient tracking bandwidth → negligible tracking error
Well-defined sampling instant (asserted by clock rising/falling edge)
Zero track-mode and hold-mode offset errors

9. T/H Errors (Track Mode)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
T/H Errors (Track Mode)
Finite tracking bandwidth → tracking error, T/H memory
Track-mode offset, gain error, and nonlinearity

10. Acquisition Time (tacq)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Acquisition Time (tacq)
Accuracy
tacq
1% (7b)
≥ 5t
0.1% (10b)
≥ 7t
0.01% (13b)
≥ 9t
Short L, thin tox, large W, large Vov, and small Vi help reduce Ron

11. T/H Errors (T-to-H Transition)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
T/H Errors (T-to-H Transition)
Pedestal error (often signal-dependent) resulted from switch turn-off
nonidealities (clock feedthrough and charge injection)
Aperture delay – the delay Δt b/t hold command and hold action
Aperture jitter – the random variation in Δt (i.e., sampling clock jitter)

12. Switch Non-Idealities
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Switch Non-Idealities
Clock feedthrough (CF)
Charge injection (CI)
Fast turn-off
Slow turn-off

13. Pedestal Error of Top-Plate T/H
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Pedestal Error of Top-Plate T/H
Slow turn-off:
Fast turn-off:
Watch out for nonlinear errors!

14. Speed-Accuracy Tradeoff of T/H
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Speed-Accuracy Tradeoff of T/H
Pedestal error:
TBW:
Therefore:
Technology scaling improves T/H performance!

15. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Aperture Delay (Δt)
Fixed aperture delay is usually not of problem in a single-path T/H
Non-uniform aperture delays among time-interleaved T/H paths cause significant errors (Δt1, Δt2… are also called sampling clock skew)

16. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Aperture Jitter
Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed sampling systems,” IEEE Journal of Solid-State Circuits, vol. 25, issue 1, pp , 1990.

17. Aperture Jitter  Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Aperture Jitter 

18. Aperture Jitter Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Aperture Jitter

19. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
T/H Errors (Hold Mode)
Hold-mode droop caused by off-switch/diode/gate leakage
Hold-mode input feedthrough (i.e., due to capacitive coupling)

20. Evaluating T/H Performance
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Evaluating T/H Performance
kT/C noise:
T = 300K CS
√kT/C
100pF
6.4μV
1pF
64μV
10fF
640μV
SNDR:
Noise
Distortion
Jitter

21. MOS S/H Techniques Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
MOS S/H Techniques

22. Simple Top-Plate Sampling
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Simple Top-Plate Sampling
Pros
Simple, minimum number of devices
Potentially wideband, zero track-mode offset
Cons
Signal-dependent tracking bandwidth
Signal-dependent charge injection and clock feedthrough
Signal-dependent aperture delay (sampling point)

23. Signal-Dependent Aperture Delay
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Signal-Dependent Aperture Delay
Non-uniform sampling due to signal-dependent aperture delay causes distortion in top-plate S/H
Sharp clock edge and small Vin mitigate the delay variation

24. Signal Distortion  ← 2nd-order
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Signal Distortion
← 2nd-order 

25. CMOS Switch Ron still depends on Vin and is sensitive to N/P mismatch
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
CMOS Switch
Ron still depends on Vin and is sensitive to N/P mismatch
Large parasitic cap due to PMOS switch for symmetric Ron
Clock rising/falling edge alignment

26. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Clock Bootstrapping
Constant gate overdrive voltage VGS = VDD for the switch
Ron is not dependent on Vin to the first order (body effect?)
NMOS device only with less parasitic capacitance

27. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Clock Bootstrapping
Ref: A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC,” IEEE Journal of Solid-State Circuits, vol. 34, issue 5, pp , 1999.

28. Clock Bootstrapping (Φ=0)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Clock Bootstrapping (Φ=0)

29. Clock Bootstrapping (Φ=1)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Clock Bootstrapping (Φ=1)

30. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Dummy Switch
Initial size of dummy chosen with the assumption of a 50/50 split of Qch; usually (W/L)dummy < ½(W/L)switch in practice
The nonlinear dependence of CI on Zi, CS, and clock rise/fall time makes it difficult to achieve a precise cancellation
Ф_ rising edge must trail Ф falling edge

31. Balanced Switch + Dummy
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Balanced Switch + Dummy
TBW
Parasitics
Ref: L. A. Bienstman and H. J. De Man, “An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling,” IEEE Journal of Solid-State Circuits, vol. 15, issue 6, pp , 1980.

32. Fully-Differential T/H
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Fully-Differential T/H
E.g.
fin
0.5GHz
VDD
1.8V tf
0.1ns
A (Vin)
0.5V
SDR (SE)
20-30 dB
SDR (DF)
40-50 dB
All even-order distortions cancelled, including the signal-dependent aperture delay-induced distortion
Actual cancellation limited by P/N mismatch (1-10% typically)

33. Bottom-Plate Sampling
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Bottom-Plate Sampling
AC-ground switch opens slightly earlier than input switches
Signal-independent CF and CI of switch Φe to the first order!
Input switch can be further bootstrapped
Typical for applications of more than 8-bit resolution
Less tracking bandwidth due to more switches in series
Signal swing at node X is not entirely zero!

34. Sample-and-Hold Amplifier (SHA)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Sample-and-Hold Amplifier (SHA)

35. Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Inverting SHA
Inverting, closed-loop gain determined by the ratio CS/CH
CMOS or bootstrapped switches are required when passing signals with large swing (where?)

36. Inverting SHA (Track-Mode)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Inverting SHA (Track-Mode)
CF and CI are independent of Vin and cancelled differentially
Φ1e switch is equivalent to two switches of half channel length → faster, less CF and CI

37. Inverting SHA (Hold-Mode)
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Inverting SHA (Hold-Mode)
CM?
DM?
For 1X gain (CS = CH), the feedback factor is about 1/2
Floating switch Φ2 in hold-mode → flexible input common mode
Useful for single-ended to differential conversion

38. Differential Mode  DM half circuit DM charge transfer is complete
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Differential Mode
DM half circuit 
DM charge transfer is complete

39. Common Mode  CM half circuit CM charge is not transferred!
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Common Mode
CM half circuit 
CM charge is not transferred!

40. Flip-Around SHA Non-inverting, 1X closed-loop gain
Data Converters Sample-and-Hold Professor Y. Chiu
EECT Fall 2014
Flip-Around SHA
Non-inverting, 1X closed-loop gain
Close-to-unity feedback factor in hold mode
CF/CI independent of Vin and cancelled differentially