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Virtex II Pro based SoPC design
Part 1 Introduction
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Before we start… The guidance consists of two parts: Introduction
SoPC concept Working platforms Design Flow – building basic system Advanced topics Adding user cores Debug (ChipScope) JTAG Simulation Today
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Outline SoPC design concept SoPC platform SoPC implementation flow
Memec design board ML310 design board Virtex II Pro Architecture PPC architecture Processor Buses SoPC implementation flow
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Introduction and SoPC platform
Part 1 Introduction and SoPC platform
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System evolution Time Old systems Recent systems Modern systems
Components of the system reside on single chip. On-chip interconnect System complexity and density All components reside in relatively small box. On-board interconnect Components of the system are large. “In-room” interconnect We are here Time Old systems Recent systems Modern systems
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SoC glossary IP (Intellectual Property) – In integrated circuits, predefined large functions, called “cores”, that help the user complete a large design faster Soft IP (soft core) – A synthesizable IP which can be readily incorporated into an FPGA Hard IP (hard core) – An IP which placed on FPGA during fabrication process and resides there all the time
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SoC design process Choose chip with required hard cores inside
Add required soft cores Add user logic
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SoC platform System on Chip System On Programmable Chip System On Chip
Application Specific Integrated Circuit Field Programmable Gate Array We are here
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SoPC platform - inside Virtex II Pro FPGA (XC2VP7)
~1M ASIC gates 44 18x18-bit Multipliers 88 KB of on-chip memory Power PC 4.05 CPU core 4 2.5Gbps Rocket I/O transceivers 4 DCM (digital clock manager) units There are more power configurations
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SoPC platform - outside
Virtex II Pro FPGA resides on Memec Development board, including: 32 MB of SDRAM 100MHz & 125 MHz clocks 2x16 LCD panel 8 user DIP switches 4 user leds 4 user push buttons Serial port interface JTAG port Hardware debugger port Extension to P160 card
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SoPC platform - outside
P160 communication card includes, in addition to resources available on board: 8M of Flash memory 1M of SRAM memory Ethernet 10/100 port USB port Additional serial port PS / 2 port External LCD interface
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ML310 development board
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Virtex II Pro architecture overview
Configurable logic block (CLB)
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB)
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver Digital Clock Manager (DCM)
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver Digital Clock Manager (DCM) Power PC CPU core
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Virtex II Pro architecture overview
Configurable logic block (CLB) Input Output Block (IOB) 18 Kb Block RAM 18x18 bit multiplier 2.5 Gbps Rocket I/O transceiver Digital Clock Manager (DCM) Processor block Global and local routing
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Block SelectRAM+ (BRAM)
44 blocks of 18 Kb each True dual-port RAM Fully synchronous Parity bits can be used Possible configurations: DIA DIPA ADDRA WEA WNA SSRA DOA CLKA DOPA DIB DIPB ADDRB WEB ENB SSRB DOB CLKB DOPB 16K x 1 bit 2K x 9 bits 8K x 2 bits 1K x 18 bits 4K x 4 bits 512 x 36 bits
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Processor block overview
CPU-FPGA interfaces 405 Core Control Logic OCM controller OCM Controller BRAM FPGA CLB Array Interface Logic Processor Block = CPU core + Interface Logic + CPU-FPGA interface
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On-chip Memory (OCM) Controller
OCM controller is designed to provide very quick access to a fixed amount of instruction and data memory space OCM controller is of a distributed style and it is split into 2 blocks Instruction Side OCM (ISOCM) Data side OCM (DSOCM) Instruction Side OCM: 64-bit read only bus (two instructions per cycle) Can support 128 KB of BRAM (if available on FPGA) Writing to ISBRAM during BRAM initialization only Data Side OCM: 32-bit data read and 32-bit data write buses Can support 64 KB of BRAM (if available on FPGA) Writing to DSBRAM during BRAM init, by CPU, FPGA via second port OCM is not cacheable memory !
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On-chip Memory (OCM) Controller
405 Core Data Side BRAM: Transient data storage Bi-directional data transfer Packet Processing D Side Controller BRAM Soft IP in Fabric Instruction Side BRAM: Boot code Interrupt Service Routines Deterministic low latency I Side Controller BRAM Fixed Logic
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PPC 405 Core organization 5-stage pipeline Memory Management Unit
Fetch Decode Execute Write-back Load write-back Memory Management Unit Separate Instruction and Data cache units Debug support, including a JTAG interface Three programmable timers
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PPC 405 Core parts - CPU 5-stage pipeline
3-element fetch queue : 2 prefetch buffers + decode buffer Static branch prediction Execution unit consist of GPR, MAC and ALU 32 32-bit registers with 3 read and 2 write ports Floating point operations are not supported! Single-cycle throughput in MAC instructions
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PPC 405 Core parts - Interrupts
Critical and non critical interrupts are supported Caused by: Error conditions Internal timers Debug events External interrupt controller (EIC) interface 2 EIC interrupts are supported
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PPC 405 Core parts - MMU 4 GB of flat address space
Multiple page sizes supported 1KB to 16MB pages (8 types) Software controlled 64 entries fully associative TLB Storage attributes are provided to control access of memory regions
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PPC 405 Core parts - Caches Independent instruction and data caches
16-KB, 2-way set associative, 32 byte line Non-blocking caches LRU replacement policy Write through / write back DCU Both have PLB master interface
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PPC 405 Core parts – Debug Four debug modes JTAG debug interface
Internal-debug : software debuggers External-debug : JTAG debuggers Debug-wait : interrupt servicing during processor appears to be stopped Real-time trace : instruction trace tools JTAG debug interface
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SoPC architecture Our SoPC based on CoreConnect standart
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CoreConnect bus architecture
Processor Local Bus (PLB) 32-bit address, 64-bit data Separate read and write buses High performance Low load On-Chip peripheral bus (OPB) 32-bit address, 32-bit data Max peripherals High load Device Control Register bus (DCR) 32-bit transfer to and from GPR Direct accessible by PPC
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The PLB and OPB buses The PLB can be thought of as the “Motorway” of the CoreConnect bus structure The PLB is fast and has a very high bandwidth There is a direct connection to the processor from the PLB The OPB can be thought of as the “A Road” of CoreConnect The OPB is a lower bandwidth bus designed to accommodate the needs of slower peripherals (UARTS, GPIO, etc.) Use of the OPB allows the PLB to remain free of the slower traffic and thus work more effectively There is no connection to PPC from the OPB The two buses are connected by an “OPB Bridge” – just like a motorway junction
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The DCR bus The DCR bus in not used to carry any sort of data which can be processed by the execution units, nor does it carry instructions DCRs (the registers themselves, not the bus) can be thought of as “flags”. These flags can be set to define the operating mode for processor peripherals. E.g. criticality of interrupts, DMA channel control, UART communication modes etc. DCR registers exist outside of the core, so the DCR bus is used to communicate with with registers
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Processor block interfaces
The processor block provides I/O signals grouped functionally into the following interfaces: PLB interface 32-bit address and three 64-bit data buses DCR interface Attachment of on-chip registers for device control Clock and Power Management (CPM) JTAG port Debugging On-chip interrupt controller Critical and non-critical interrupts On-chip memory controller Reset interface Three types of reset
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SoPC design using XILINX Tools
Part 2 SoPC design using XILINX Tools
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Hardware / Software flow
How is Embedded system created? Hardware design flow Software design flow Integration Embedded development Kit (EDK) Assists in creating system hardware definition Calls XILINX ISE for FPGA implementation Assists in creation of software code GNU Cross Compiler / Debugger (GCC / GDB) XILINX Microprocessor Debugger (XMD)
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SoPC Design Tool Chain Standard Software Flow Standard Hardware Flow
VHDL / Verilog C/C++ code Simulator Compiler / Linker Synthesizer Object code Place & Route .elf .bit Data2BRAM PPC code in on-chip memory PPC code in off-chip memory Download to FPGA Debugger Download to FPGA Chip Scope Pro Tools
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Design Debug (HW and SW)
Where does EDK assist? Hardware Flow Software Flow HW Block diagram SW flow chart EDK HW description Create SW source ISE Synthesize, P&R Compile DATA2BRAM Bit file / download Elf file / download Design Debug (HW and SW)
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Using BSB to create new project
Base System Builder is wizard helping you build system in easy way
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Using BSB to create new project
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Using BSB to create new project
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Using BSB to create new project
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Creating project without BSB
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Project directory structure
Must be without spaces Projects directory name Current project name This directory will typically contain user c and h files code Here ucf (user constraint file) resides data User defined cores should be placed here pcores Drivers for user defined cores should be placed here drivers Files needed for simulation sim Here will be compiled and linked code (elf) ppc405 code include Files generated during software flow lib Additional directories are created after synthesis
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EDK main window System block diagram System description Message window
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System description System cores Main files
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EDK- Hardware flow Specify processor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA
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Specify cores Choose core version
Address space must be specified if needed
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Specify buses Specifying master / slave interface on the bus(es)
Specifying BRAM port
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Connecting components
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Changing cores generics
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Hardware flow - MHS Microprocessor Hardware Specification file
Specify processor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA Microprocessor Hardware Specification file A text file that describes the hardware structure Processor Bus architecture Peripherals Connectivity of the system Address space
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Hardware flow - MPD Microprocessor Peripheral Definition file
Specify processor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA Microprocessor Peripheral Definition file Template that specifies ports and parameters of IP List ports and default connectivity for bus interfaces List parameters and default values Any MPD parameter is overwritten by equivalent MHS assignment
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Hardware flow – Platform generator
Platform Generator (Platgen) Uses MHS and MPD files to create hardware platform Creates HDL wrappers Creates netlist files (EDF, NGC) Creates support files for downstream tools Specify professor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA
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Hardware flow – Implementation
Implementation flow XFlow Batch mode place & route flow ProjNav ISE Project Navigator place & route flow Specify professor, bus and peripherals, hardware configuration Automatic HDL files generation Xilinx implementation flow Bitstream Download to FPGA
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EDK – software flow After peripheral hardware definition, the software is independent on the hardware flow Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Download to FPGA Data2BRAM Bitsream Hardware flow Execute in off-chip memory Execute in on-chip memory GDB / XMD
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Software flow - MSS Microprocessor Software
Specification Auto-generated / user modifiable Contain all project software options Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Download to FPGA Data2BRAM Bitsream Hardware flow Execute in off-chip memory Execute in on-chip memory GDB / XMD
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Software flow - MDD Microprocessor Driver Definition
Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Microprocessor Driver Definition Describes configurable parameters in a driver Defines driver dependencies
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Software platform settings
Double click on any peripheral to open software settings window OS : standalone, VxWorks, Linux, xilkernel
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Software platform settings (2)
Frequency: used for different time-related functions Should be set to actual h/w frequency (100 Mhz)
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Software platform settings (3)
Definition of standard I/O, i.e. printf and scanf will be mapped to these devices
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Software applications
Memory parameters of the application (default start address is 0x0, default heap + stack size is 400 bytes) Software code to be downloaded to memory
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Adding source files
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Software flow – Code compilation
Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable After software compilation ELF file is created Executable and Linking Format
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When software meets hardware …
The contents of .bit file (hardware) can be updated with contents of .elf file (software) downloadable .bit file DATA2BRAM .elf file (software) (hardware) .bit file describes hardware platform, BRAM contents undefined .bmm file .bmm file maps defined BRAM memory to actual BRAM blocks here .bit file describes hardware platform with BRAM contents updated with program code BRAM Memory Map
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Software flow – Library generator
Specify Software Architecture Automatic software BSP / Library generation Software compilation Executable Directory Structure after executing the Libgen Command: code folder will contain the user output program file (executable.elf) include folder contains header files for this design libsrc folder contains source files for the drivers used in this design lib folder contains standart C, Math and Xilinx libraries
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Downloading to the board
Downloading the bitstream to hardware can be accomplished one of to ways: With the EDK With the ISE iMPACT
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Tools invocation Libraries generation Netlist generation Data to BRAM Code compilation Bitsream generation Downloading bitsream After software changes, Data2BRAM can be performed without re-generating of bitsream To run all the flow enough to invoke “Data2BRAM” or “Downloading bitsream” When using ProjNav, “bitsream generation” icon is inaccessible
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Essential links EDK Tutorials
Virtex II Pro architecture (FPGA, BRAM, DCM, Multipliers) PPC405 block architecture (OCM, processor I/O interfaces) PowerPC processor architecture (inside) PLB, OPB and other cores Information can be found by opening PDFs from the EDK EDK, drivers, adding user cores, MicroBlaze processor In addition, all the information is on the Q:\Virtex II Pro
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Summary - demonstration
System including next components will be demonstrated: PPC405 processor 32K of PLB BRAM PLB2OPB bridge 16K of OPB BRAM 32M of OPB SDRAM OPB GPIO for interface with leds, switches, push buttons and lcd OPB UART for interface with computer Simple program runs on PPPC405
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System block diagram PPC405 PLB bus OPB bus FPGA JTAG port Reset block
RST BRAM PPC405 JTAG interface BRAM controller PLB bus BUS arbiter PLB to OPB bridge OPB bus BUS arbiter BRAM controller GPIO GPIO UART SDRAM controller DIP switches Push buttons LCD LEDs Hyper Terminal BRAM SDRAM Off-chip
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System build flow Hardware flow – platform build
Add required cores to the design -> peripherals Define address space for BRAM, SDRAM, GPIOs, UART, OPB -> peripherals Connect PPC and one of BRAMs to PLB, all the other cores to OPB -> bus conn. Define external ports (UART rx, tx, SDRAM address and data etc.) Connect internal ports by signals (connect clock to all cores, connect JTAG block to PPC etc.) -> ports Define generics for cores where it is required (for example, UART baud rate) -> parameters Choose port A BRAM connection for both BRAMs -> bus conn.
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System build flow Hardware flow – platform generation
Choose XPS design flow (Project Options window) Generate netlist Define platform (previous slide) Define pins in ucf file Generate bitstream (system.bit file)
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System build flow Software flow
Define UART as standard I/O peripheral for PPC Define level 1 drivers for GPIO and level 0 for other cores Write simple C program Define operating system as standalone, core freq. 100 Mhz. and location for output elf file For running from BRAM, define program start address 0xFFFF8000 (BRAM resides at this address) Compile program For running from SDRAM, define program start address 0x0 (SDRAM resides at this address) Generate libraries
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Download to FPGA from EDK
System build flow Run Data2BRAM download.bit file is created Implementation Download via iMPACT download.bit file For running from BRAM Run XMD Download via iMPACT system.bit file Download via XMD executable.elf file For running from SDRAM
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MicroBlaze based SoPC architectire
Appendix A MicroBlaze based SoPC architectire
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MicroBlaze buses Local Memory bus (LMB) On-Chip Peripheral bus (OPB)
Appendix A MicroBlaze buses Local Memory bus (LMB) 32-bit high speed memory access Single-cycle to on-chip BRAM ILMB (Instruction LMB) DLMB (Data LMB) On-Chip Peripheral bus (OPB) 32-bit processor interface 8/16/32-bit peripheral interface IOPB (instruction OPB) DOPB (data OPB)
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