1. TEL62 firmware live kick-off meeting Mainz September 2011

2. Get together and head count General overview of firmware requirements Working environment and collaboration Functionalities and rough partitioning Work sharing and time schedule Today

3. Firmware development for the TEL62 must be a collaborative effort: Pisa will drive it, but contribution by at least 1 person per sub-detector is essential (need not be a firmware expert, but somebody willing to devote time to this) Mostly centered on TDC-daughtercard operation (but identify common blocks usable for LKr/L0 operation) Any sub-detector could be (in principle) L0-triggering or not Firmware will likely be (slightly) different for different sub- detectors: strictly confine sub-detector differences in few well- identified blocks. Generalities

4. Use a common development environment Firmware must be centrally stored, consistent, modular, scalable and understantable to others besides the author Strict name-space and memory-space constraints Documentation is not an optional feature to be provided “later”, it must come with the code Each firmware module must be simulated and should come together with its own test bench code Live testing and diagnostic features should be incorporated General principles

5. The firmware is to be controlled – initialized – monitored from the CCPC (access during data taking possible) Use only low-level libraries from LHCb (JTAG, glue, I2C, …) with frozen source code Command-line control program (with scripting and macros) made available by Pisa: - tightly linked to firmware version - to be customized for sub-detector firmware versions - to be used both for test/monitoring and real data-taking - initialization via XML files Scientific Linux version: to be frozen TEL62 firmware loading requires JAM-file player: existing LHCb version not working: to be solved – Perugia Software

6. PP0 PP1 PP2 PP3 SL CCPC (CPU) GLUE TTCrx Quad GbE QDR DDR AUX Daughter card (TDCB) TEL62

7. DDR control Data formatter and writer Data extraction Trigger handling Trigger primitive generator Core services & monitoring Inter-PP communication Daughtercard comm Daughtercard DDR Prev PPNext PP SL PP-FPGA Data correction

8. QDR control Data formatter and writer Gbit handling TTCrx & trigger handling Core services & monitoring AUX board communication PP0 PP1 PP2 PP3 QDR TTCrx SL-FPGA Data merger Trigger primitive merger Trigger primitive handling Gbit Prev TEL62Next TEL62

9. Run under Windows Use SVN with remote (CERN?) repository Choose tool versions and freeze to them Software tools Mentor Graphics HDL Designer Same tools as LHCb (newer versions): Altera Quartus II (v. 11 needed)

10. HDL Designer Steep learning curve (reading the manual might help) Interfaces to other tools (e.g. Modelsim simulator, Quartus) Hybrid graphical and VHDL (and Verilog) programming Allows simulation of the entire board (several FPGAs + other modules) Integrated versioning system (CVS, SVN, etc.)

11. Firmware tree

12. PP-FPGA SL-FPGA Sub-detector specific versions later: pp_rich, pp_lav, etc. Sub-detector specific versions (if needed) later: sl_rich, sl_lav, etc.

13. TEL62 Possible alternate version for LKr/L0 Common and sub-detector memory spaces

14. DDR control Data formatter and writer Data extraction Trigger handling Trigger primitive generator Core services & monitoring Inter-PP communication Daughtercard comm Daughtercard DDR Prev PPNext PP SL PP-FPGA Pisa Perugia Unassigned (*) (*) RICH version Data correction

15. QDR control Data formatter and writer Gbit handling TTCrx & trigger handling Core services & monitoring AUX board communication PP0 PP1 PP2 PP3 QDR TTCrx SL-FPGA Data merger Trigger primitive merger Trigger primitive handling Gbit Prev TEL62Next TEL62 Pisa Perugia Unassigned

16. PP SL DDR TDC Gbit QDR TTCrx CCPC GLUE (ECS) Simulation blocks Pisa

17. ItemNotesLHCb?WhoStatus Core & monitoringRegisters, memories, clocks, spy YES/NOPisaStarted Live test blocksData transfer testsNOPisaStarted Daughter-card commFor TDCBNOPisaStarted Data correctionOffsets, data manipolationNO Data formatter/writerTime framing, countingNOPisa DDR controlBurst writing/reading, arbitrationNOPisaStarted Data extractionTimestamp translation, framingNOPisa Trigger handlingTrigger type handling, arbitrationYES/NOPisa Trigger primitive genRICH version (time multiplicity) Can be different for other SD NOPerugiaStarted Inter-PP commTrigger primitive exchangeNO PP-FPGA FIRMWARE BLOCKS

18. ItemNotesLHCb?WhoStatus Core & monitoringRegisters, memories, clocks, spy YES/NOPisaStarted Live test blocksData transfer testsNOPisa Data mergerMerge 4 PP dataYES Data formatter/writerMulti-event packetsYES Gigabit controlEthernet (as in TELL1 + receiver) YES/NO QDR controlBurst writing/reading, arbitrationYESPisa Trig primitive mergerMerge 4 PP trigger dataNO Trig primitive handling Merge other board trigger data, format, send to Gbit NO TTCrx handlingTimestamps, trigger type, resetsYES/NOPisa AUX-board handlingInter-board communicationNO SL-FPGA FIRMWARE BLOCKS

19. ItemNotesLHCb?WhoStatus TDC simulation block NOPisaStarted DDR simulation blockNOPisa QDR simulation blockNOPisa TTCrx simulation blockYES/NOPisa CCPC simulation blockYES/NOPisa Gbit simulation blockYES/NO AUX cardDesign and building-- JTAG test vectors--Roma 2 OTHER TASKS