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Published byJalynn Whitely Modified over 9 years ago
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Read-Write Memories (RAM)
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 6-transistor CMOS SRAM Cell
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM CMOS SRAM Analysis (Write)
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM CMOS SRAM Analysis (Read)
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 1-Transistor DRAM Cell
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM DRAM Cell Observations
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 1-T DRAM Cell
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Periphery
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Dynamic Decoders
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 4 input pass-transistor based column decoder
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM 4-to-1 tree based column decoder
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Sense Amplifiers
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Differential Sensing - SRAM
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Latch-Based Sense Amplifier
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Open bitline architecture
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM DRAM Read Process with Dummy Cell
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Open Bit-line Architecture —Cross Coupling
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Alpha-particles
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Yield Yield curves at different stages of process maturity (from [Veendrick92])
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Redundancy
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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM Redundancy and Error Correction
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