1. 1 Pertemuan 13 Memory Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2. 2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menerapkan gerbang logik, switching logik, dan atau struktur deskripsi Verilog untuk membangun sistem memory sederhana dalam CMOS VLSI.

3. 3 Static Memory World line MAL MAR bit wl MAL bit MAR bit wl V DD MAL bit MAR bit wl V DD General SRAM cell 6T cell CMOS SRAM circuit 4T cell CMOS SRAM with poly resistor

4. 4 Static Memory 2 bit_1 Wl_1 V DD bit_2 Wl_2 2 port CMOS SRAM cell

5. 5 SRAM Arrays D 0 D 1 D 2 D n-3 D n-2 D n-1 a 0 a 1 a m-2 a m-1 N x n array WE En control address data I/O High level view SRAM bit wl Single cell Row driver Row (world line) decoder Row driver Column decoder MUX Left core Right core Central SRAM block architecture

6. 6 SRAM Arrays d N-1 d0d0 d0d0 d1d1 d1d1 d2d2 d2d2 d3d3 d3d3 WL_0 WL_1 WL_2 WL_3 WL_4 WL_5 Cell arrangement in a core region

7. 7 SRAM Arrays 5 A m-1 A m-2 A 3 A 2 A 1 A 0 Address Latch Column decoder Row decoder Column select (y) Row select (x) Basic Addressing Scheme

8. 8 SRAM Arrays Precharge Sense amp I/O  Data in Data out WE En 

9. 9 Dynamic RAMs Bit line World line WL V power + - Vs Storage capacitor Mn Access FET 1T DRAM cell WL=1 + - Vs ON Input Vd Write operation WL=0 + - Vs OFF Hold

10. 10 Dynamic RAMs V max Charge leakage in a DRAM cell WL=0 + - Vs ILIL V1V1 0 th Minimum logic 1 voltage t

11. 11 ROM Arrays Read Only Memories (ROM) are used for permanent bit storage. The structure of a ROM array is similar to that used for RAMS. However, the data cannot be alltered once the chip is fabricated. Electrically programmable ROMs PROMs) allow the user to store data as required by the application. Special voltage settings are used to write to the cells.

12. 12 RESUME Static memory: static RAMs Arrays. Dynamic RAMS. ROM Arrays.