1. An Efficient Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints Rupesh S. Shelar Intel Corporation Hillsboro, OR 97124 Prashant Saxena Synopsys Inc Hillsboro, OR 97124 Xinning Wang Intel Corporation Hillsboro, OR 97124 Sachin S. Sapatnekar University of Minnesota Minneapolis, MN 55455 International Symposium on Physical Design San Francisco April 5, 2005

2. 2 Outline Introduction Algorithm Overview Congestion Map Generation Slack-constrained Covering Results & Conclusion

3. 3 Motivation  Technology Scaling  Routing resources growing at same rate?  Upper metal layers for global signals  Resistive (i.e., wide) wires  Result: Routing Congestion

4. 4 Targeting Routing Congestion  Can be alleviated during routing, placement, technology mapping, and logic synthesis  Limited flexibility during P & R points to technology mapping  Mapping decides wires Design Freedom Placement RTL Routing Technology Mapping

5. 5 Previous Work  Structural logic synthesis Adhesion metric, Kudva et al.,TCAD’03 Computationally expensive  Congestion-aware Technology Mapping using Wirelength, Stok et al., ICCAD’01, Pandini et al.,TCAD’03 –“ … a purely top-down single-pass congestion-aware technology mapping is merely wishful thinking.’’ Mutual contraction (MC), Liu et al., ISPD’05 Predictive probabilistic congestion, Shelar et al., TCAD’05 –Congestion map based on subject graph

6. 6 Outline Introduction Algorithm Overview Congestion Map Generation Slack-constrained Covering Results & Conclusion

7. 7 Problem Definition  Minimize routing congestion under delay constraints during technology mapping  Dynamic programming for delay constraints  Routing congestion: captured by track overflow and max. congestion  Minimize total track overflow under delay constraints

8. 8 Employing Placement-level Metric  Wirelength and mutual contraction cannot capture track overflow  Predictive probabilistic congestion map can Same congestion map for different choices  Can we instead employ placement-/routing-level metric? Technology Mapping Placement Routing RTL Predictive PCM, Mutual Contraction, Wirelength Probabilistic CM (PCM) Congestion Map (CM) Estimation Error

9. 9 Probabilistic Congestion Map  Probabilistic congestion map, a post-placement metric Lou et al., TCAD’02; Westra et al., ISPD’04 Pin 2 Pin 1 1 2 3 4 5 6 All routes equally possible: Probability of any route =1/6 1/12 3/12 5/12 3/12 1/12 2/12 1/12 2/12 1/12 3/12 5/12 3/12 1/12

10. 10 “Chicken-and-Egg” Problem  Overflow computation requires congestion map Available after mapping  Track overflow of a wire depends on other cones also Overflow due to Wire 1 depends on Wire 2 and vice versa Area or delay at Wire 1 do not depend on Wire 2 Placement RTL Probabilistic CM Technology Mapping ? RTL Probabilistic CM Technology Mapping + Placement Wire 1 Wire 2

11. 11 Solution Overview  Track overflow cannot be computed incrementally, but congestion maps can. Construct congestion maps using algebraic operations  Defer track overflow computation to covering Requires congestion maps capturing all wires in mapping solutions  Overcome the “chicken-and-egg” problem: Construct congestion maps bottom-up during matching Compute track overflow during covering

12. 12 Outline Introduction Algorithm Overview Congestion Map Generation Slack-constrained Covering Results & Conclusion

13. 13 The Matching Phase  Store the load-delay curve containing non-inferior delay matches Performed for all nodes in topological order  Compute congestion map for each non-inferior match Load Delay L1L1 L2L2 M1M1 M2M2 M3M3 D1D1 D2D2 M1M1 M2M2 M3M3 C unknown

14. 14 Algebraic Addition for Congestion Maps N2N2 N3N3 N1N1 M1M1 1.25 0.75 0.00 0.75 0.25 0.00 0.50 1.00 0.00 0.25 0.50 0.25 0.00 0.50 1.25 1.00 0.25 0.50 0.25 0.75 1.00 0.75 + + =

15. 15 Handling Multiple Fanouts  For forward propagation, divide congestion maps by the number of fanouts Allows correct computation of maps for solutions at PO’s N1N1 N2N2 N3N3 0.2 0.8 0.4 0.2 0.4 0.6 0.1 0.4 0.2 0.1 0.2 0.3

16. 16 Congestion Map Generation  Congestion map for a match at a node represents wires from the fan-in cone only  Add congestion maps for matches at PO’s to get congestion map for an entire solution  Extensible to congestion based on fast global routing  Applicable to generation and propagation of any 2-D maps, e.g., power-density map

17. 17 Outline Introduction Algorithm Overview Congestion Map Generation Slack-constrained Covering Results & Conclusion

18. 18 Exploiting Slacks  Classical covering: choose an optimum delay match For C load =15, M 2 is optimal with Delay = 50  Assume: slack of 10 M 1 and M 3 also satisfy delay constraints  Allow non-delay-optimal matches on non-critical paths M 1 or M 3 preferred if the corresponding overflows smaller Load Delay 10 20 M1M1 M2M2 M3M3 10 3 2 1 M1M1 M2M2 M3M3 15 40 60

19. 19 Slack-constrained Covering  Compute delays and slacks at the primary outputs (PO’s) due to delay-optimal solution  Compute corresponding congestion map  For all nodes in reverse topological order, –Compute delay and track overflow due to delay- optimal and congestion-optimal matches –If congestion-optimal match exists, store it –Else, store delay-optimal match –Propagate updated slacks to inputs of match

20. 20 Extensions and Complexity  Slack-constrained covering applicable for Different cost functions, e.g., maximum congestion Traditional objectives, e.g., area, power  Time complexity Linear in number of nodes (for a fixed library and layout area) Run-times practical  Memory complexity High memory requirement due to congestion map storage for all matches –Asymptotically same as conventional Memory efficient variants possible Current implementation applicable up to ~5,000 cells Ideal for ECO mode hot-spot (re-)synthesis

21. 21 Outline Introduction Algorithm Overview Congestion Map Generation Slack-constrained Covering Results & Conclusion

22. 22 Experimental Setup  Mapping algorithm incorporated in SIS  Capo for placement  Timing driven routing  ISCAS’85 benchmarks  100 nm process parameters from Predictive Technology Model  Library: enhanced lib2.genlib with up to 4 strengths for each gate  Experiments on 400 MHz Sun Ultra Sparc 60  Comparison with conventional mapping in SIS Subject Graph Placement Routing Timing Analysis Technology Mapping

23. 23 Track Overflow Comparison

24. 24 Maximum Congestion Comparison

25. 25 Delay Comparison

26. 26 Row-utilization Comparison

27. 27 Run-time Comparison

28. 28 Summary of Experimental Results  Track overflows: 44% better  Delays: no adverse impact  Maximum congestion: 25% better  Row-utilization: no significant correlation  Run-times: 2x worse, but still practical

29. 29 Conclusion  Presented a delay-optimal mapping algorithm to minimize routing congestion  Validated effectiveness on benchmark circuits  Algorithmic framework applicable for optimization of other cost functions and properties  Future directions Implementation of memory efficient version Placement-legalization based flow Application to ECO-mode logic (re-)synthesis

30. 30 Backup

31. 31 Analogy with Classical Matching  Mapping for area optimization under delay constraint, Chaudhary et al., TCAD’95  Similarities The gate-area for a match at a given node represents gates only due to the nodes in the fan-in cone Similarly, congestion map for a match at a given node represents wires due to the nodes in fan-in cone Gate-area divided at multiple fanout points Congestion-maps divided at multiple fanout points  Differences Ensures delay optimality Wire-delays accounted for in the delay computation Routing congestion more complex than gate-area

32. 32 Experimental Results Ckt.Area (μ 2 )RU (%)Overflow (Gain %)Delay (ps) C1355343980 81227 134 40789 786 C1908361680 323 225 301059 1042 C26701170775 77417 167 591258 1240 C35402599475 801078 294 721655 1632 C432196280 8266 49 25854 842 C499355080 79262 135 48823 821 C53151726575 771100 289 731120 1114 C62882137980 515 452 124771 4731 C75522822375 731343 547 591341 1309 C880394480 76378 260 31890 884 Avg.78 554 255 441455 1439

33. 33 Experimental Results (Continued) Ckt.MC# of CellsRun-time (s) C13551.70 1.30621 59211 12 C19081.70 1.40578 57112 13 C26701.65 1.201482 142624 51 C35402.25 1.403254 310590 279 C4321.40 1.20264 3117 9 C4991.60 1.20595 56311 13 C53152.20 1.402122 213138 121 C62881.70 1.403737 359688 135 C75521.60 1.303198 3080132 213 C8801.70 1.20584 57512 13 Avg.1.74 1.291640 159542 85