1. Electronics Modification: Critical Design Delta Review 2 Tom Montagliano July 27 th, 2012 1

2. Open Items Modifications 1.Perform noise measurement on larger scale 2.Zoom into noise data and analyze 3.Determine how current will be measured with Virgo attached 4.Re-select protection diode that will not allow voltages over 5.7 V 5.Gather more information on temperature sensor and develop action plan 6.Re-simulate crosstalk with proper values for the input voltage 7.Propose PCB layout, schematic and mounting 2

3. Noise analysis with varied time scales Critical Design Delta Review 2 3

4. Noise analysis with different time scales on plot 4 x-axis=ADU y-axis = time (ms) measurements made with current source added CDS noise = 9.84 µV measurements made with no current source CDS noise = 8.88 µV

5. Diode Selection Critical Design Delta Review 2 5

6. Diode selection 1.The Vishay 5.65 V zener diode (TZX5V6D) is an ideal choice for our application since there is little current draw at 5V and the voltage drop will not exceed 5.7 V. 2.The Fairchild 5.6 V zener diode (1N5343BTR) is not as good as the Vishay diode for our application since there is relatively more current draw at 5V. 3.With 5 V on the bias line, the voltage across the diode will be 4.95 V for the Vishay diode and 4.87 V for the Fairchild diode. 4.CONCLUSION: The Vishay 5.65 V zener diode (TZX5V6D) will be used as the protection diode. 6

7. Temperature Sensor Critical Design Delta Review 2 7

8. Temperature Sensor 1.There is 1 DT470-SD-12A located on the motherboard of the Virgo package. 2.This will be routed to the Lakeshore through the cabling and will not involve the electronics system. 8 DT470-SD-12A

9. Crosstalk Simulations Critical Design Delta Review 2 9

10. Notes on Source-follower Transimpedance 1.It was suggested to assume R DS(on) = 2 kΩ, BUT: 2.Using this value results in bogus simulation results (flat lines) 3.PSPICE parameter “RDS”:PSPICE parameter “RDS” a.Description: “Drain-source shunt resistance” b.Units: ohms; Default value: infinity 4.We know that an ideal MOSFET acting as a switch will have R DS = 0 Ω 5.Recall small-signal model of PMOS FET: a.Ideally r o = infinity; so in PSPICE, R DS must be the same as r o. b.The source/drain impedance when FET is “on” is a combination of g m, V GS, and r o. We don’t know this information without physical testing, or information from Raytheon. 1.For these simulations, we’re using an ideal PMOS FET http://www.prenhall.com/howe3/microelectronics/pdf_folder/lectures/mwf/lecture12.fm5.pdf

11. Measured R out of Leach +16.5 V VLVL R L (Ω)V L (V)I L (mA)R out (Ω) Inf.16.5850.0n/a 1737.416.5829.54410.314 259.1616.575563.95860.1485 147.516.572112.35250.1157 1.Measure V L with no load (V OC ) 2.Measure R L and add R L to circuit. Measure V L. 3.Calculate I L = V L / R L. 4.Calculate R out = (V oc – V L ) / I L.

12. Schematic 100 KHz square wave with 10 ns rise/fall-time

13. Voltage Measurements Aggressor Victims Efficiency of Source Follower: Duration of crosstalk to within 25 µV PP : (10.11 – 10.0) = 0.11 µs After 0.11 µs, V PP = 4.29 µV. f max > 2 MHz (assuming 25 µV PP takes 0.5 µs).

14. Current Measurements Aggressor Victims I PP = 54.9 nA I PP = 14.5 pA t = 10.11 µs – 10.01 µs = 100 ns

15. Schematic with Bypass Capacitors

16. Voltage Measurements with Bypass Capacitors Aggressor Victims Duration of crosstalk to within 25 µV PP : 0.0 ns f max limited by rise/fall times V PP = 2.86 µV

17. Crosstalk Conclusions 1.The voltage supply output resistance should be as small as possible to reduce voltage droops a.If R out = 0 Ω: no crosstalk b.If R out = 10 Ω: crosstalk is as previously shown c.Measured R out ≈ 0.1 Ω 1)Crosstalk will be much less than what was previously shown 2.Adding small (0.1 µF) bypass capacitors to each current source significantly reduces crosstalk to the point of insignificance

18. Current Source Board (CSB) schematic, layout and mounting Critical Design Delta Review 2 18

19. CSB schematic 19

20. CSB layout 20 potentiometer SMT JFET Through Hole JFET 0 ohm resistor SMT resistor

21. General procedure for measurement of calibration of a single current source 1.Remove 0 Ω resistor from CSB 2.Ensure potentiometer is at maximum value 3.Connect ammeter using vias on CSB 4.Run System so that current source is active 5.Adjust potentiometer until 200 µA is measured on ammeter 6.Turn off system 7.Reinstall 0 Ω resistor 21

22. CSB Mounting Side View (Actual Size) 22

23. CSB Mounting Side View 23 ARC46 board in adjacent slot Capacitor on bottom : 4.5 mm 5/8” 4-40 screws Mating DB connector MOD BRACKET ARC46 board PCB DB connector Current Source Board 1/8” Spacer Potentiometer : 5 mm 16.5 V Supply Through Hole Resistor: 1.5 mm Current Source Board wire connection to PCB

24. CSB Mounting Top View (Actual Size) 24

25. CSB Mounting Top View 25 5/8” 4-40 screws Mating DB connectors MOD BRACKETS ARC46 board PCB DB connectors Current Source Board Potentiometers 16.5 V Supply pInput through hole locations on the ARC-46 (not on CSB) Mounting Holes

26. Mod Bracket Specifications 26 Top View Front ViewRight Side View 4-40 tapped screw hole 4-40 clearance 1.673” 0.250” 0.303” 0.531” 0.750” 0.236” 0.0625” 0.100”