1. Copper Damascene Plating Process Development Engineer
1/5/06
Brandon Brooks
Process Development Engineer
Semitool Confidential

2. Outline Why Cu Interconnects? Damascene Process Flow
Parameters Affecting Cu Interconnects
Backside Clean and Bevel Etch

3. Damascene Plating?
The damascene in Cu damascene plating refers to the inlay of gold or some other metal into a substrate.

4. Al Cu Interconnect Metal Properties Best!  Resistivity  Resistivity
Why Cu Interconnects?
Interconnect Metal Properties Al Cu W
Melting Pt (°C)
660
1,083
3,410
Oxidation in Air
Rapid; Self-Sealing
Slow; Not Self-Sealing
Inert
Resistivity (mW-cm)
Crystalline
2.82
1.77
5.6
As Deposited *
8-11
Self-Diffusion Coefficient 100 °C
2.1·10-20
2.1·10-30
Coefficient of Thermal Expansion (Unit/°C)
24·10-6
17·10-6
4.3·10-6
* Alloy (Si, Cu)
Best!
 Resistivity
 Melting Point
Thermal Expansion
Electromigration Cu
 Resistivity
 Melting Point
Thermal Expansion
Electromigration Al
Al was the metal of choice for chip interconnects up until the late 90s. There are still many chipmakers that are using Al for their interconnect metal, but as feature sizes shrink, more fabs are making the switch to Cu.
Cu offers several benefits over Al. Al is very prone to electromigration. Electromigration is the movement of metal atoms with e- flow. Over time electromigration will lead to breaks in the line causing shorts in the metal interconnect. Also Al has a high resistivity, which leads to decreased performance from RC delay in the circuit.
Because of these characteristics, Cu was the natural choice to replace Al. Cu has a low Rs and strong resistance to electromigration, as well as a higher melting point and decreased thermal expansion when compared to Al. These characteristics make Cu a higher performance and more reliable choice for interconnect metal.

5. Interconnect Metal Properties
Why Cu Interconnects?
Interconnect Metal Properties Al Cu Ag
Etch Properties
Cl & Br Plasmas
F & Cl Plasmas
Etch Rate (Å/min)
5,000
500
Cu has a very slow etch rate
Cu halides are solid at normal temperatures
Changing from Al to Cu interconnects requires new process flow
Enter Damascene plating
When chipmakers were using Al interconnects, they could use a subtractive metal etch process to form the Al interconnects. However, the halide plasma that was used to etch Al interconnects couldn’t be used on Cu because Cu halides are solid at room temperature. Thus a new process flow for metal interconnects had to be approached. This new approach became known as Damascene plating. It was called damascene because instead of forming the interconnect lines from the subtractive etch of the metal, the metal interconnect was inlayed into features that were formed by the subtractive etch of dielectric instead.

6. Typical Damascene Process Flow
Dielectric Deposition
Photoresist Deposition
UV Exposure
Develop Photoresist
Etch Dielectric
Remove Photoresist
Barrier Deposition
Seed Layer Deposition
Electrochemical Deposition (ECD)
Backside Clean and Bevel Etch
Anneal
Chemical Mechanical Polish (CMP)
Repeat Steps 1-10 for Every Metal Layer
Today’s Main Topics
This is a simplified process flow for the formation of Cu damascene interconnects. I have a movie that will show this process flow, but I will focus on steps 7-12 for the majority of the presentation.

7. Damascene Process Flow
Negative Resist: Usually Dry-Film and UV Exposure Hardens
Positive Resist: Usually Liquid Spin On and UV Exposure Softens

8. Key Factors Affecting Cu Interconnect Performance
Copper Interconnect Parameters
Key Factors Affecting Cu Interconnect Performance
Gap-Fill
CD Uniformity
Overburden
Anneal
There are 4 key factors that determine Cu interconnect performance:
Gap-fill refers to how well we fill the trench with Cu. Our goal is to completely fill the trench without voiding.
Uniformity and Overburden are parameters that affect the subsequent process in the damascene interconnect flow, which is CMP. And finally, Anneal refers to the thermal recrystalliztion of the the Cu film, which leads to increased Cu grain size.
AMD’s 9 Cu Levels

9. Key Parameters for Gap-Fill
Copper Interconnect Parameters: Gap-Fill
Key Parameters for Gap-Fill
Seed and Barrier Layers
Uniformity
Thickness
Plating Recipe
Hot Start (Initiation)
Fill Current Density
Waveform
Plating Chemistry
Inorganic
Organic
0.12m, 8.3:1AR Trenches
The first parameter that affects gap-fill is the seed and barrier layer uniformity and thickness. These parameters are very important and our part of the previous process in the flow. Without good seed and barrier layers, then we cannot deposit a good Cu film.
The second parameter affecting gap-fill is the plating recipe. There are 3 main portions to the recipe: Hot start, which refers to the initial entry of the wafer into our plating chemistry. Fill current density, which refers to the amount of current passed through the wafer during gap-fill. And Waveform, which refers to the power setting of the current used to plate the Cu on the wafer.
The third paramter affecting gap-fill is plating chemistry, which has both inorganic and organic components.
ECD Seed plus Nanoplate ECD Cu

10. Physical Vapor Deposition (PVD) Effects
Copper Interconnect Parameters: Gap-Fill
Seed and Barrier Layers
Physical Vapor Deposition (PVD) Effects
The seed and barrier layers are deposited using a PVD process. The PVD chamber’s main features are a target made of the metal to be deposited and a chuck that holds the wafer directly under the target. In the PVD process, high energy Ar ions bombard the target, which is made of the metal to be deposited. This ion bombardment causes metal ions to fall off of the target and fall to the wafer surface.
The barrier is deposited first. The function of the barrier is twofold, to provide a barrier to the diffusion of Cu into the dielectric and to provide adhesion between the dielectric and metal interconnect.
The seed is deposited second. Its function is to provide an electrical contact for the ECD process.
This PVD process is a line of sight process, which leads to some issues. It is very difficult to get good sidewall coverage in the trench. Usually the bottom of the trench and the top of the trench are covered well, but the sides of the trench are harder to cover. If you have too thick of a barrier or seed, then this will lead to an increased overhang, which will cause pinch off during the ECD process.
You also need to have as uniform as possible coverage of the sidewall, if there is poor sidewall coverage, then it will lead to sidewall voiding in the ECD process.

11. Edge Shadowing Optimized Seed Layer Seed and Barrier Layer Uniformity
Copper Interconnect Parameters: Gap-Fill
Seed and Barrier Layer Uniformity
The left SEM image shows sidewall voiding due to excessive edge shadowing, while the right image has no voiding because of the good sidewall coverage.
Edge Shadowing
Optimized Seed Layer

12. 1500Å Total Seed Thickness 2000Å Total Seed Thickness
Copper Interconnect Parameters: Gap-Fill
Seed and Barrier Layer Thickness
1500Å Total Seed Thickness
2000Å Total Seed Thickness
0.30micron, 4.8:1 AR Vias
The left image in this slide shows an optimized seed layer, while the right image shows seam voiding due to pinch off in the ECD step caused by too much overhang from the PVD step.

13. 2X Fill Rate on the 2V Hot Start
Copper Interconnect Parameters: Gap-Fill
Plating Recipe Hot Start
2X Fill Rate on the 2V Hot Start
No Hot Start
2V Hot Start
0.180 m Line Width Trenches
48 Coulombs ECD

14. The Effect of Current Density upon Gap Fill
Copper Interconnect Parameters: Gap-Fill
Plating Recipe Current Density
Current too Low
Current too High
The Effect of Current Density upon Gap Fill
Bad
Good
0.35μm, 4.3:1 AR Vias
0.18μm, 5.1:1 AR Trench
Gap Fill
Current Density
Low
High
Optimum Fill
for feature D
Optimum Current
When the current density is too low, then the organic portion of the bath doesn’t function properly and we get insufficient gap-fill. When the current density becomes too high, then we become mass transport limited on Cu and we get insufficient gap-fill.

15. DC plating provides better additive adsorption
Copper Interconnect Parameters: Gap-Fill
Plating Recipe Waveform
Waveform
Cu Diffusion
Additive Adsorption
Bottom Up Fill
Direct Current (DC) - +
Pulse DC
Pulse Reverse (PR)
DC plating provides better additive adsorption
Pulsed plating provides better Cu diffusion

16. Inorganic Components Organic Components Copper Sulfate (CuSO4)
Copper Interconnect Parameters: Gap-Fill
Plating Chemistry
Inorganic Components
Copper Sulfate (CuSO4)
Hydrochloric Acid (HCl)
Sulfuric Acid (H2SO4)
Organic Components
Suppressor (PEG)
Accelerator (SPS)
Leveler (Amine)
Suppressor is generally a polyethlyene glycol compound. Accelerator is generally a sulfopropyl-disulfide compound. Leveler is an amine containing polymer

17. Copper Effect on Gap Fill
Copper Interconnect Parameters: Gap-Fill
Inorganic Plating Chemistry
Copper Effect on Gap Fill
High Copper
Low Copper
From Linlin’s high cu bath work. Top Picture is Nanoplate POR bottom is high Cu bath. Dependency of gap fill on Cu is for a specific plating conditions. The lower the current density or with PR plating the weaker the correlation. We have seen similar results looking at diluted baths compared to the POR

18. Chloride Effect on Gap-Fill
Copper Interconnect Parameters: Gap-Fill
Inorganic Plating Chemistry
Chloride Effect on Gap-Fill
A minimum concentration( around 35-40ppm) of Chloride ions is required to gain maximum suppression (optimum gap fill). Beyond this there is not much effect on gap fill unless the concentration is very high. However, those conditions are not well defined.

19. Acid Effect on Gap Fill Inorganic Plating Chemistry pH 3 pH 2 pH 2
Copper Interconnect Parameters: Gap-Fill
Inorganic Plating Chemistry
pH 3
pH 2
Acid Effect on Gap Fill
pH 2
Acid gives throwing power (conductivity). The more acid in the bath, the higher the current will be for a given potential. Also, the greater the amount of acid in the bath, the better the organic molecules will work.

20. Organic Effect on Gap Fill
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Organic Effect on Gap Fill
Accelerator
Catalytic effect
Requires very small amount of Cl-
Increased current for a given potential
Suppressor
Suppresses deposition
Requires Cl- to adsorb onto copper surface
Decreases current for a given potential
Leveler
Suppresses deposition at high current density areas
Very low concentration (diffusion limited)

21. Cyclic Voltammetric Stripping Analysis (CVS)
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Cyclic Voltammetric Stripping Analysis (CVS)
Stripping Region A C B
A = VMS
B = VMS + Suppressor
C = VMS + Sup. & Accel. I
Plating Region
In CVS analysis, we sweep the voltage from positive to negative potential on a platinum rotating disk electrode in electrolyte. This voltage sweeping subsequently plates and strips a small amount of Cu from the electrolyte onto the platinum RDE. We then graph the current as a function of potential of the RDE and integrate the area under the stripping curve to calculate how much Cu was plated. V

22. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
0.1
0.2
0.3
0.01
0.02
0.03
0.04
0.05
Suppressor
Concentration
80 g/l
Low Acid (10g/l)
High Acid 150 g/l 5 10 15 20 25 30 1 2 3 4
Accelerator
80 g/l H2SO4
Worse
Better
Stripping Area
This is important because many of the additives in the bath are more effective with higher acid concentrations. This CVS plot show that with higher acid, the suppressor in Enthone’s Viaform chemistry are more effective passivators and the Accelerators more effective at increasing plating rates. This results in improved superfill characteristics.
For a given Suppressor or Accelerator concentration, the higher the acid concentration, the better they work to perform gap-fill.

23. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Blue = Suppressor bonded to a Cl
Red = Additive
Green = Leveler

24. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Initial deposition is conformal. Notice that the leveler molecule has started to electrostatically adhere to the top corner of the trench due to the higher effective current density at these areas.

25. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
As bottom corners close in accelerator begins to concentrate in the bottom of the feature due to the reduction in the surface area inside of the trench.

26. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
The increased concentration of accelerator in the bottom of the feature facilitates bottom up gap-fill.

27. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Note: the concentration of additive on the top of the filled feature. This leads to over bumping.

28. Organic Plating Chemistry
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry

29. Key Parameters for Current Density Uniformity
Copper Interconnect Parameters: CD Uniformity
Key Parameters for Current Density Uniformity
Chemistry
High Acid
Low Acid
CFD Reactor
Electric Field Control
Uniformity in this case refers to both uniformity of current density and uniformity of the ECD Cu deposit
Intel: 8 Cu Levels

30. Generalized Electrochemical Schematic
Copper Interconnect Parameters: CD Uniformity
Generalized Electrochemical Schematic
Electrolytic Copper Deposition
Ammeter V0 +
Current Density = Current
Surf. Area
Current Path e- e-
Electrolyte
Cu2+
Cu2+
This is a simplified soluble anode schematic.
Surface
Area
Cu0  Cu2++2e-
Cu2++2e-  Cu0
Anode
(Oxidation)
Cathode
(Reduction)

31. Rcat Relec V Ranode= 0 Rcat  1/Seed Thickness Rcat  Wafer Radius
Copper Interconnect Parameters: CD Uniformity
Relec  1/Bath Conductivity
Rcat  1/Seed Thickness
Rcat  Wafer Radius
Relec
Ranode= 0 V +
Electrolyte
Cathode
(Thin)
Anode
(Thick)
Rcat
= Surface Area
= Area
V=IR
If you take a section of wafer with the same surface area at the center and edge of the wafer, then the amount of current passing through the wafer at the edge and center are given by the following equations.

32. How To Make Small? V Rcat Relec Rcat Current Density Throughput
Copper Interconnect Parameters: CD Uniformity
How To Make
Small?
Relec
Ranode= 0 V +
Electrolyte
Cathode (Thin)
Anode (Thick)
Rcat
Edge
I Loop
Center V
Current Density
Throughput
Rcat
Seed Layer Thickness
Wafer Radius
Relec
Bath Conductivity
If you decrease voltage, then you mess with a critical gap-fill parameter, current density, as well as throughput capability. You can decrease your cathode resistance by increasing your seed layer thickness or decreasing your wafer diameter, both of which are the exact opposite of what happens when the technology node shrinks. The only thing left is to increase your electrolyte resistivity by decreasing the bath conductivity, which minimizes, but does not fix the problem.

33. Conductivity at Various Bath Conditions
Copper Interconnect Parameters: CD Uniformity
Conductivity at Various Bath Conditions
100
200
300
400
500
600
Conductivity (mS/cm)
175 g/l H2SO4
17 g/l Cu
80 g/l H2SO4
50 g/l Cu
10 g/l H2SO4
“Low” Acid
“High” Acid 70
247
511
At higher acid concentrations, Cu is less soluble. So if we decrease the bath conductivity we have tampered with 2 critical parameters for gap-fill. Cu concentration and acid concentration. So if we run an ECD process in a conventional single anode system, then we will not be able to run the best chemistries.

34. Terminal Effect Current Density Wafer Radius Plating Time
Copper Interconnect Parameters: CD Uniformity
Terminal Effect
0sec
5sec
15sec
30sec
60sec
120sec
Current Density
Wafer Radius
Plating Time
(0,0)
This difference in current from the center to the edge of the wafer is refered to as the terminal effect. The terminal effect cause a huge difference in the current density from the center to the edge of the wafers. As you can see, this difference dissipates over time as the Cu film thickness increases. By the end of plating, the CD is essentially equal from center to edge.

35. The Effect of Current Density upon Gap Fill
Copper Interconnect Parameters: CD Uniformity
Current too Low
Current too High
The Effect of Current Density upon Gap Fill
Bad
Good
0.35mm, 4.3:1 AR Vias
0.18mm, 5.1:1 AR Trench
Gap Fill
Current Density
Low
High
Optimum Fill
for feature D
Optimum Current
As you will remember from before, Current density is a critical parameter for gap-fill as well.

36. receiving the same process?
Copper Interconnect Parameters: CD Uniformity
Are the center and edge
receiving the same process?
This terminal effect then leads to differences in the type of process that a trench in the center of the wafer and a trench on the edge of the wafers is subject to. So, in a conventional reactor, we can have poor gap fill in the center and good on the edge or vice versa, due to this varying current density from the center to the edge.

37. V1 V2 Advanced Reactor Design: Multiple Anodes
Copper Interconnect Parameters: CD Uniformity
Advanced Reactor Design: Multiple Anodes
Robust system that can handle multiple chemistries
Built for the future with the ability to handle shrinking die size
Cost effective ability to handle increasing wafer diameters
V1 and V2 adjusted until
Independent of Rc and Relec
Cathode
Anode 2 V1 + V2 1
Enter the multi-anode CFD reactor. By having multiple anodes, we effectively negate differences in current density from the center to the edge of the wafer by changing the potential of the anodes to give a uniform current density from the center to the edge of the wafer. The difference in current becomes independent of the chemistry and seed layer thickness that we use.

38. Conventional Reactor CFD Reactor
Copper Interconnect Parameters: CD Uniformity
Dielectric
Electrolyte
Virtual Anodes
Physical Anodes
Wafer
Conventional Reactor
CFD Reactor

39. Rotating Wafer Overflow Electrolyte Virtual Anode Bubble Trap
Copper Interconnect Parameters: CD Uniformity
Concentric
Annular Anodes
Electrolyte
Bubble Trap
Rotating Wafer
Dielectric
Flow Inlet
Overflow
Virtual Anode

40. Superposition of Electric Field
Copper Interconnect Parameters: CD Uniformity
Superposition of Electric Field
-120
-100
-80
-60
-40
-20 20 40 60 80
100
120
Wafer Diameter (mm)
Normalized Voltage at Cathode (V)
Anode 1
Anode 2
Anode 3
Anode 4
Summed Field

41. 133% <5% 20% <5% SEMITOOL - CFD Conventional High Acid Low Acid
Copper Interconnect Parameters: CD Uniformity
100 nm Seed layer, 1m deposition
Conventional
SEMITOOL - CFD 14 18 22 26 30 34
Current Density (mA/cm^2)
0sec
5sec
15sec
30sec
60sec
120sec
133%
<5%
High Acid
511mS/cm 14 18 22 26 30 34 25 50 75
100
125
150
Current Density (mA/cm^2)
0sec
120sec
20% 25 50 75
100
125
150
<5%
Low Acid
70mS/cm
Wafer Radius (mm)

42. Dynamic Compensation for Constant Current Density
Copper Interconnect Parameters: CD Uniformity
Dynamic Compensation for Constant Current Density
1.0
1.5
2.0
2.5 20 40 60 80
100
120
Deposition Time (sec)
Anode Current (Amps)
Anode 2
Anode 3
Anode 1
Anode 4
Current density is a function of time and wafer radius. Semitool’s 4-anode reactor allows us to dynamically change the currents to provide a uniform current density from the beginning to end of ECD.

43. Key Parameters for Overburden
Copper Interconnect Parameters: Overburden
Key Parameters for Overburden
Local Overburden (Overplating) – Fill Step
Chemistry
3-Component
2-Component
Waveform
Direct Current
Pulse Reverse
Global Overburden – Cap Step
High Acid
Low Acid
CFD Reactor
There are 2 types of Overburden: Local and Global. Local overburden refers to the step height of Cu between an area of sparsely occupied or even blanket features and an area of very dense features. Global overburden refers to the amount of copper that is plated after complete gap-fill and is taken off during CMP. Combinations of these 4 factors lead to differing amounts of local overburden.

44. 3-Component Organic Package Pulse Reverse POR Step Up No Step Up
Copper Interconnect Parameters: Local Overburden
Direct Current POR
3-Component Organic Package
Moderate Acid Electrolyte
Pulse Reverse POR
2-Component Organic Package
High Acid Electrolyte
Step Up
No Step Up
Pulse Reverse Waveform leads to less overburden during the fill step. In order to achieve the same results with DC, higher concentrations of Leveler need to be used.

45. Planar Deposition Overplating
Copper Interconnect Parameters: Local Overburden
Insufficient Leveler
Planar Deposition
Optimized Organic Conditions
Overplating
Post-CMP Residual Cu
No Post-CMP Residual Cu
Pulse Reverse Waveform leads to less overburden during the fill step. In order to achieve the same results with DC, higher concentrations of Leveler need to be used.

46. Thickness Variation (Å)
Copper Interconnect Parameters: Global Overburden
-100mm
100
-800
-600
-400
-200
200
400
600
800Å
Radial control of
Thickness Variation (Å)
Cu Thickness (Å)
The multiple anode design of the CFD reactor lends itself to applying
Wafer Diameter (mm)

47. Raider CFD Profile Before & After 30s CMP
Copper Interconnect Parameters: Global Overburden
Raider CFD Profile Before & After 30s CMP
16,000
12,000
CFD Profile before CMP
Thickness (A)
8,000
Uniform Post-CMP Profile
Profile after 30s CMP
4,000
POR Profile Before & After 30s CMP
16,000
The Semitool CFD reactor allows users to profile the global overburden to compensate for CMP nonuniformity.
12,000
POR Profile before CMP
Thickness (A)
Early
Clearing!
8,000
Profile after 30s CMP
4,000
Edge
Residual!
Wafer Diameter

48. Copper Interconnect Parameters: Global Overburden
CMP Profile Matching

49. Key Parameters for Anneal
Copper Interconnect Parameters: Anneal
Key Parameters for Anneal
Temperature
Feature Size
Barrier Layer
The least resistive Cu film is composed of the larger grained Cu. Grain orientation also, plays a role, but the Cu film that has the smallest grains will undoubtedly have the higher resistance. The higher the resistance, then the slower electrons will travel through the interconnect and the slower your device will be. Thus, we anneal after ECD to grow the Cu crystals.

50. Effect of Temperature Small Grains Large Grains As Deposited
Copper Interconnect Parameters: Anneal
Effect of Temperature
As Deposited
Self Annealed
Thermally Annealed
Small Grains
Large Grains
High temperature is necessary to completely anneal Cu inside of device features.

51. Effect of Feature Size Self-Anneal Furnace Anneal 1.0m Trenches
Copper Interconnect Parameters: Anneal
Effect of Feature Size
1.0m
Trenches
0.25m
Trenches
As feature size increases, grain growth is easier.
Self-Anneal
Furnace Anneal

52. Effect of Barrier Layer
Copper Interconnect Parameters: Anneal
Effect of Barrier Layer
Ta Barrier Layer
TiNx Barrier Layer
Strong Surface Interaction
Reduced Migration
Weak Surface Interaction
Increased Migration
Large Voids

53. Optimum Anneal Condition
Copper Interconnect Parameters: Anneal
Optimum Anneal Condition
Anneal Temp
Line Resistance Ta
TaNx
TiNx
Grain Growth
Void Formation
Optimum

54. Why Backside Clean and Bevel Etch?
Cu is a highly mobile ion
Backside contamination can have adverse effects across the fab
Unstable films on the edge of the wafer can cause surface damage at CMP
Objective
Remove bulk Cu on the edge of the wafer
Delamination
Flaking
Yield Problems
Remove atomic Cu on the back of the wafer
Common Photolithography
Common Metrology
Cu ion diffusion

55. Capsule 1 Chamber Cut Away
Backside Clean and Bevel Etch
Capsule 1 Chamber Cut Away
Edge Exclusion Hardware
Capsule 1 Features
Hardware control of bevel etch (BE)
0-4mm BE edge exclusion (EE) range
No front side protection needed
BE & backside clean simultaneously
Clean N2 purged microenvironment
Hardware sets capable of 1 to 3 mm bevel etch

56. Capsule Dynamics Front Side Inlet: Wafer Device Up Back Side Inlet:
Backside Clean and Bevel Etch
Capsule Dynamics
Wafer
Device Up
Seal
Chamber Rotation
Back Side Inlet:
-Dilute Piranha Solution
DI H2O N2
Front Side Inlet:

57. Capsule Dynamics Front Side Inlet: Wafer Device Up Back Side Inlet:
Backside Clean and Bevel Etch
Capsule Dynamics
Seal
Chamber Rotation
Back Side Inlet:
-Dilute Piranha Solution
DI H2O N2
Front Side Inlet:
Wafer
Device Up

58. Precision Control of Chemical Wrap-Around
Backside Clean and Bevel Etch
Precision Control of Chemical Wrap-Around
A concentric 1.5mm EE BE clears the notch
Critical Bevel Etch Parameters
Concentricity
Complete Cu Clearing
Clearing the Notch

59. Precision Control of Concentricity
Backside Clean and Bevel Etch
Precision Control of Concentricity
Concentricity Spec (a) ≤ 0.2mm

60. Precision Control of Copper Removal
Backside Clean and Bevel Etch
Precision Control of Copper Removal
E Beam Spot Magn WD 10 µm
10.0kV x STI. Bevel Etch
No Copper on Edge Exclusion Zone
No undercut
Target ECD 1.0µm
1 µm ECD Copper
1.5 mm Edge Exclusion
Profilometer Reading
52º Tilt on SEM
<10 µm

61. Summary Why Cu Interconnects? Damascene Process Flow
Resistivity
Reliability
Damascene Process Flow
Photolithography to CMP
Parameters Affecting Cu Interconnects
Gap-Fill
Current Density Uniformity
Overburden
Anneal
Backside Clean and Bevel Etch
Bulk Cu on the Edge
Atomic Cu on the Backside

62. Acknowledgements John Klocke – Cu Damascene Group Leader
Kevin Witt – Cu Damascene Business Development Leader
Tom Ritzdorf – Director of ECD Technology
Jake Cook – Marketing Communications
All Semitool personnel that have contributed data to this presentation
Many of you probably have seen some of your own work in this presentation, so if you did, I thank you for your contributions. Thanks.