1. Device Microelectronic Prof. Dr. Ir. Djoko Hartanto MSc Jurusan Elektro Fakultas Teknik Universitas Indonesia Semester Genap 2003

2. SAP  SKS: 3  Staf Pengajar  PJ: Prof. Dr. Ir. Djoko Hartanto MSc. (DH)  Ang: Arief Udhiarto, ST. (AU)  Sistem Kelas: Tunggal  Sistem Evaluasi (dalam %)  (20) Tugas.  (30) Midtest,  (30) UAS,  (20) Seminar

3. TanggalPokok Bahasan dan Isi BahasanMedia*TugasDosen 1. 04-02-021.Pre-test 2.The development of IC 3.Processing Overview Power- Point (PP) Topics for Seminar, Design Model Device-Fab., Journals. DH 2. 07-02-02Thermal Oxidation of Silicon-1 1.Properties of matters 2.Kinetics of Oxidation PPDH 3. 11-02-02Thermal Oxidation of Silicon-2 1.Oxide Thickness Charts 2.Preparation of Thermal Oxide PPHomework (HW) –1 Calculation of depth diffusion DH 4. 14-02-02Thin Film Deposition 1.Evaporation 2.Chemical Vapor Deposition PPDH 5. 18-02-02Lithography –1 Photomasks Photoresists PPCollect HW-1DH 6. 21-02-02Lithography-2 Resolution Linewidth PPDH 7. 25-02-02Etching-1 1.Wet Etching 2.Dry Etching PPHW-2 Resolution / linewidth Problems DH 8. 28-02-02Etching-2 1.Plasma Etching 2.Vapor Phase Etching PPDH 9. 04-03-02Epitaxy 1.Vapor Phase Epitaxy 2.Liquid Phase Epitaxy PPCollect HW-2DH

4. 10. 07-03-02Diffusion-1 1.Atomic Diffusion Mechanisms 2.Diffusion Characterization DH 11. 11-03-02Diffusion-2 1.Diffusion Processes 2.Diffusion Equipments PPDH 12. 14-03-02Diffusion-3 1.Diffusion Sources 2.The Error Function PPDH 13. 18-03-02Diffusion ProfilePPDH 14. 21-03-02Ion ImplantationPPAU 15. 25-04-02Ohmic Contact Schottky Barriers PPAU 16. 28-04-02InterconnectPPDH 17. 01-04-02MAGIC-1PPAU 18. 04-04-02MAGIC-2PPAU 19. Lihat Jadwal Midtest MidtestDH, AU 20. 15-04-02Laboratory visitAU

5. 21. 22-04-02SPICES-1AU 22. 25-04-02SPICES-2PPAU 23. 29-04-02SUPREM-1PPAU 24. 02-05-02SUPREM-2PPAU 25. 06-05-02Seminar-1PPAU 25. 09-05-02Seminar-2PPAU 26. 13-05-02Seminar-3PPAU 27. 20-05-02Seminar-4PPAU 28. 23-05-02Seminar-5PPAU 29. Lihat Jadwal Ujian Akhir Final TestDH, AU

6. Pre-Test 1.Sebutkan empat tahap utama dalam proses microchip fabrication ! 2.Apa yang dimaksud dengan photolithography? 3.Apa fungsi packaging dalam proses pabrikasi?

7. Terms and Concepts to be Covered in this Lesson siliconsilicon substratesubstrate monocrystallinemonocrystalline polycrystallinepolycrystalline epitaxial silicon growthepitaxial silicon growth polysiliconpolysilicon silicon dioxidesilicon dioxide oxideoxide silicon nitridesilicon nitride metalmetal dopantdopant dopingdoping concentrationconcentration diffusiondiffusion field effect transistorfield effect transistor source, drain, gatesource, drain, gate

8. Terms and Concepts to be Covered in this Lesson MOSMOS NMOS technologyNMOS technology n-channeln-channel PMOS technologyPMOS technology p-channelp-channel CMOS technologyCMOS technology p-wellp-well n-welln-well photoresistphotoresist photomaskphotomask exposureexposure diffusiondiffusion thin filmsthin films photolithographyphotolithography etchetch ion implantion implant polish, CMPpolish, CMP planarizationplanarization strips and cleansstrips and cleans test and sorttest and sort

9. Variations in Dopant Concentrations ConcentrationP-typeN-type lightly dopedp-n- very lightly dopedp--n-- heavily dopedp+n+ very heavily dopedp++n++

10. Processing Overview Tahap-tahap pabrikasi chip IC 1.Material Preparation Convert silicon dioxside to semiconductor-grade silicon 2.Crystal Growth and Wafer Preparation Convert polysilicon to silicon wafer  Crystal growing  Slice cutting and polishing  Photomask manufacturing

11. Procesing Overview 3.Wafer Fabrication a.Cleaning of surfaces b.Growth of epitaxial layer c.Thermal oxidation of silicon d.Patterning of the various layers (lithography) e.Diffusion of impurities into silicon f.Ion implantation of impurities

12. 12 Wafer Fabrication g.Chemical vapor deposition of polycristalline silicon h.Etching of silicon and GaAs i.Deposition of insulating layers (silicon oxide or nitride) j.Etching of insulating layers (silicon oxide or nitride) k.Depositon of conductive layers (metal, polysilicon, other) l.Alloying (sintering) to form metal-silicon electrical contact

13. Wafer Fabrication m.Backgrinding (thinning of wafer by grinding) n.Multiprobing (DC electrical testing of each IC on wafer)

14. 4. Packaging a.Cutting or breaking of wafers into individual chips b.Packaging of individual chips c.Full AC dan DC electrical testing of packaged ICs

15. Fabrication process of a simple metal oxide semiconductor (MOS) transistor silicon substrate source drain gate oxide oxide top nitride metal connection to source metal connection to gate metal connection to drain polysilicon gate doped silicon field oxide gate oxide

16. The manufacture of a single MOS transistor begins with a silicon substrate. silicon substrate

17. A layer of silicon dioxide (field oxide) provides isolation between devices manufactured on the same substrate. silicon substrate oxide field oxide

18. Photoresist provides the means for transferring the image of a mask onto the top surface of the wafer. silicon substrate oxide photoresist

19. Shadow on photoresist photoresist Exposed area of photoresist Chrome plated glass mask Ultraviolet Light silicon substrate oxide Ultraviolet light exposes photoresist through windows in a photomask.

20. Shadow on photoresist photoresist Exposed area of photoresist Chrome plated glass mask Ultraviolet Light silicon substrate oxide Ultraviolet light exposes photoresist through windows in a photomask.

21. Exposed photoresist becomes soluble and can be easily removed by the develop chemical. Unexposed area of photoresist silicon substrate Exposed area of photoresistoxide photoresist

22. Unexposed photoresist remains on surface of oxide to serve as a temporary protective mask for areas of the oxide that are not to be etched. Shadow on photoresist silicon substrate oxide photoresist photoresist

23. Areas of oxide protected by photoresist remain on the silicon substrate while exposed oxide is removed by the etching process. silicon substrate oxide oxide photoresist

24. The photoresist is stripped off -- revealing the pattern of the field oxide. silicon substrate oxide oxide field oxide

25. A thin layer of oxide is grown on the silicon and will later serve as the gate oxide insulator for the transistor being constructed. silicon substrate oxide oxide gate oxide thin oxide layer

26. The gate insulator area is defined by patterning the gate oxide with a masking and etching process. silicon substrate oxide oxide gate oxide

27. Polysilicon is deposited and will serve as the building material for the gate of the transistor. silicon substrate oxide oxide gate oxidepolysilicon

28. The shape of the gate is defined by a masking and etching step. silicon substrate oxide oxide gate gate ultra-thin gate oxide polysilicon gate

29. Dopant ions are selectively implanted through windows in the photoresist mask. silicon substrate oxide oxide gate gate photoresist Scanning direction of ion beam implanted ions in active region of transistors Implanted ions in photoresist to be removed during resist strip. source drain ion beam

30. The source and drain regions of the transistor are made conductive by implanting dopant atoms into selected areas of the substrate. silicon substrate oxide oxide gate gate source drain doped silicon

31. A layer of silicon nitride is deposited on top of the completed transistor to protect it from the environment. silicon substrate source drain gate top nitride

32. Holes are etched into selected parts of the top nitride where metal contacts will be formed. silicon substrate source drain gate contact holes

33. Metal is deposited and selectively etched to provide electrical contacts to the three active parts of the transistor. silicon substrate source drain gate oxide oxide metal contacts

34. Completed structure of a simple MOS transistor silicon substrate source drain gate oxide oxide top nitride metal connection to source metal connection to gate metal connection to drain polysilicon gate doped silicon field oxide gate oxide

35. Test/Sort Thin Films Photo Implant Diffusion Etch Polish Manufacturing Areas in Wafer Fab Wafer Fabrication (front-end) Bare silicon wafer Completed product

36. Common Terms in Wafer Fab Diffusion –high temperature processes –atmospheric - low vacuum pressures –oxidation, anneal, alloy, deposition, diffusion Photolithography –patterning process (masking) –photoresist coating –exposure to UV light –develop

37. Common Terms in Wafer Fab Etch –selective removal of specific materials –permanent patterning of wafer –low vacuum - high vacuum pressure –RF power, plasma etching Ion Implant –selective doping of specific areas of wafer –through windows in photoresist or oxide –high voltage, high vacuum, ion acceleration

38. Common Terms in Wafer Fab Thin Films –moderate temperatures –low vacuum - high vacuum pressures –dielectric films, metals, anneal Polish –chemical mechanical polish (CMP) –planarization of wafer surface

39. Common Terms in Wafer Fab Strips & Cleans –dry, plasma resist strip –wet, chemical cleans using acid solutions and solvents Test/Sort –automated testing of each die on wafer –discriminate good from bad –determines a fab’s yield –ship to assembly & packaging

40. Typical Wafer Flow in CMOS Fab Thin Films Photo Implant Diffusion Etch Test/Sort Polish

41. CMOS Inverter Technology Schematic Diagram Top view of Transistor Cross-section of Transistor V DD V SS V out V in s d s d g g V DD V SS V out V in g g s d s d n-channel transistor p-channel transistor p-well n+ p+ n+ p+ n-substrate source drain source drain field oxide gate oxide metal polysilicon gate contact