1. Embedded Systems I2CI2C

2. Feature 3 wire GND SCL(clock) SDA(data) All devices share the same bus wire Using wire and, each device gain access to bus (become bus master) by arbiter protocol Speed Standard——100Kbps Fast-mode——400Kbps High-speed mode——3.Mbsp

3. Wire and structure

4. Connection of devices Single Master Multiple Master

5. Master/Slave Master is the initiator of data Tx/Rx Master drive the SCL Slave passively receive command and execute command sent by master, can only control SDA Signal

6. Start/Stop of data transfer SCL=H, falling edge of SDA indicates start of transmission SCL=H, rising edge of SDA indicates stop of transmission When transmitting data, SDA can only change when SCL=0 MSB transmitted first

7. Mast write operation Slave Acknowledge: Host Release SDA, Slave pull SDA down Slave pulldown Slave pullup if error

8. Master Write operation (detail) 1.Master generate specific start signal （ SCL ＝ H ， SDA ＝ H  L ） inform all devices, that master will transfer data 2.Master put target device address to the IIC bus, ７ -bit address + 1-bit read/write flag( １  Read, 0  Write) 3.Master release SDA waiting for target device response. 4.Target device (device with matched address) pulldown SDA for response 5.Master see response on SDA, continue transmitting data on SDA Line 6.Master release SDA after transmitting each byte, waiting for response from the target device 7.Device pulldown SDA indicating that data received correctly 8.Master continue sending data until end of data 9.Master send specific data to inform end of transmission （ SCL ＝ H ， SDA ＝ L  H ）

9. Master read operation

10. Mastre read operation (detail) 1.Master generate specific start signal （ SCL ＝ H ， SDA ＝ H  L ） inform all devices, that master request data from slave 2.Master put target device address to the IIC bus, ７ -bit address + 1-bit read/write flag( １  Read, 0  Write) 3.Master release SDA waiting for target device response. 4.Target device (device with matched address) pulldown SDA for response 5.Master receive data when target response. 6.Target send data via SDA, After sending each byte, slave release SDA, waiting for master response. 7.Master pull down SDA to response to slave that data is received correctly 8.After receiving all data. Master send specific data to inform end of transmission （ SCL ＝ H ， SDA ＝ L  H ）

11. Design Example （ EEPROM ）

12. Desing Example （ IO Expansion ）