1. Logic Families and Their Characteristics
Chapter 9
Logic Families and Their Characteristics
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2. The TTL Family Bipolar transistors Two-input NAND gate
Multiemitter transistor
Totem-pole output stage
See Figure 9-1
HIGH level output typically 3.4 V
LOW level output typically 0.3 V
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3. Figure 9-1
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4. TTL Voltage and Current Ratings
Input/Output Current and Fan-Out
source current IOH
sink current IOL
low-level input current IIL
high level input current IIH
See Figure 9-5 and 9-6
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5. Figure 9-5
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6. Figure 9-6
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7. TTL Voltage and Current Ratings
Input/Output Voltages and Noise Margin
differences between high level voltages or low level voltages
See Figure 9-7
See Table 9-1
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8. Figure 9-7
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10. Other TTL Considerations
Pulse-Time Parameters
Rise Time
from 10% up to 90% level
Fall Time
from 90% down to 10% level
Propagation Delay
tPLH and tPHL
See Figure 9-10
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11. Figure 9-10(a)
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12. Figure 9-10(b)
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13. Other TTL Considerations
Power Dissipation
total power supplied to the IC power terminals
Open-Collector Outputs
upper transistor removed from totem-pole
can sink current
can not source current
pull-up resistor used
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14. Other TTL Considerations
Wired-Output Operation
outputs from two or more gates tied together
wired-AND logic - See Figure 9-15
Disposition of Unused Inputs and Unused Gates
open inputs degrade noise immunity
on AND and NAND - tied HIGH
on OR and NOR - tied LOW
unused gates - force outputs HIGH
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15. Figure 9-15
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16. Other TTL Considerations
Power Supply Decoupling
place 0.01 to 0.1 F capacitor directly across Vcc to ground pins
reduce EMI radiation
reduce effect of voltage spikes from power supply
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17. Improved TTL Series 74HXX series Schottky TTL 74FXX
half the propagation delay
double the power consumption
Schottky TTL
low-power (LS)
advanced low-power (ALS)
74FXX
reduced propagation delay
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18. The CMOS Family MOSFETs
metal oxide semiconductor field-effect transistors
PMOS and NMOS type substrates
See Figure 9-18
higher packing densities than TTL
millions of memory cells per chip
See Table 9-2
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19. Figure 9-18
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21. The CMOS Family Handling CMOS Devices CMOS availability
avoid electrostatic discharge
CMOS availability
4000 Series - original CMOS line
40H00 Series - faster
74C00 Series - pin compatible with TTL
74HC00 and 74HCT00 Series
speedy, less power, pin compatible, greater noise immunity and temperature operating range
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22. The CMOS Family CMOS availability
74- BiCMOS Series - low power and high speed
74-Low Voltage Series
See Appendix B
supply voltage of 3.3 V
74AHC and 74AHCT Series
superior speed
low power consumption
high output drive current
Vcc or 3.3 V or 5 V
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23. The CMOS Family Advanced Very-Low-Voltage CMOS Logic faster speed
very low operating voltages
3.3, 2.5, 1.8, 1.5 and 1.2 V
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24. Emitter-Coupled Logic
Extremely fast
Increased power dissipation
Uses differential amplifiers
See Figure 9-22
Newer Technologies
integrated injection logic (I2L)
silicon-on-sapphire (SOS)
gallium arsenide (GaAs)
Josephen junction circuits
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25. Figure 9-22
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26. Comparing Logic Families
Performance Specifications
See Table 9-3
Propagation delay versus power
See Figure 9-24
Power supply current versus frequency
See Figure 9-25
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28. Figure 9-24
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29. Figure 9-25
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30. Interfacing Logic Families
TTL to CMOS
See Figure 9-26
pull-up resistor - see Figure 9-27
CMOS to TTL
See Figure 9-28 and 9-29
Worse-Case Values
See Table 9-4
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31. Figure 9-26
Figure 9-27
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32. Figure 9-28
Figure 9-29
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34. Interfacing Logic Families
Level Shifting
Level-shifter ICs
4049B and 4050B - see Figure 9-31
4504B - see Figure 9-32
ECL Interfacing
See Figure 9-33
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35. Figure 9-31
Figure 9-32
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36. Figure 9-33
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37. CPLD Electrical Characteristics
Electrical characteristics vary between manufacturers
specifications are in data sheets
MAX 7000 CPLD specifications
advanced CMOS
interface with 5, 3.3, 2.5, or .8 V devices
separate VCC pins for internal operations/input buffers and for I/O drivers
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38. CPLD Electrical Characteristics
EPM728S is part of the MAX7000S series
can interface with 5V and 3.3V devices
see figure 9-35
provide open drain output
complete TTL and CMOS compatibility
low propagation time
speed/power optimization feature
see figure 9-36
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39. Figure 9-35
Figure 9-36
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40. Summary
There are basically three stages of internal circuitry in a TTL (transistor-transistor-logic) IC: input, control, and output.
The input current (IIL or IIH) to an IC gate is a constant value specified by the IC manufacturer.
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41. Summary
The output current of an IC gate depends on the size of the load connected to it. Its value cannot exceed the maximum rating of the chip, IOL or IOH.
The HIGH- and LOW-level output voltages of the standard TTL family are not 5 V and 0 V but typically are 3.4 V and 0.2 V.
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42. Summary
The propagation delay is the length of time that it takes for the output of a gate to respond to a stimulus at its input.
The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels.
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43. Summary
Open-collector outputs are required whenever logic outputs are connected to a common point.
Several improved TTL families are available and continue to be introduced each year providing decreased power consumption and decreased propagation delay.
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44. Summary
The CMOS family uses complementary metal oxide semiconductor transistors instead of the bipolar transistors used in TTL ICs. Traditionally, the CMOS family consumed less power but was slower than TTL. However, recent advances in both technologies have narrowed the differences.
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45. Summary
The BiCMOS family combines the best characteristics of bipolar technology and CMOS technology to provide logic functions that are optimized for the high-speed, low-power characteristics required in microprocessor systems.
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46. Summary
A figure of merit of IC families is the product of their propagation delay and power consumption, called the speed-power product (the lower, the better).
Emitter-coupled logic (ECL) provides the highest-speed ICs. Its drawback is its very high power consumption.
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47. Summary
When interfacing logic families, several considerations must be made. The output voltage level of one family must be high and low enough to meet the input requirements of the receiving family. Also, the output current capability of the driving gate must be high enough for the input draw of the receiving gate or gates.
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