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Present by Pitipund Lorchirachoonkul 43650225 Uchot Jitpaisarnsook 43650373 Present by Pitipund Lorchirachoonkul 43650225 Uchot Jitpaisarnsook 43650373 Arm (Advance RISC Machine)
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RISC Overview A large uniform register file A load-store architecture Simple addressing modes Uniform and fixed length instruction fields
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Arm Overview Control over both the ALU and shifter Auto-increment and auto-decrement addressing modes Load and store multiple instructions Conditional execution of all instructions
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ARM registers 31 registers, 32-bit: 16 are visible and other are used to speed up exception processing Program counter (R15) Link register (R14) Other registers
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Types of Exceptions Two levels of interrupt Memory aborts Attempted execution of an undefined instruction Software interrupts
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ARM Instruction Set Branch Data-processing Load and store Coprocessor
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Branch Instructions General branch Intructions Branch with Link Software interrupt
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Data-processing Instructions Data-processing instructions proper Multiply instructions Status register transfer instructions
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Load and Store Instructions Load or store single register Load and store multiple register Swap a register value with the value of a memory location
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Coprocessor Instructions Data-processing instructions Register transfers Data-transfer instructions
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The CPU Core 5 stage pipeline Harvard architecture ARM v4T compliant 110,000 transistors TSMC 0.18 m: 0.3 mW/MHz (1.8V) 220MHz (1.65 V) 1 mm 2
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ARM Application
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Typical appliance that running Java application
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Jazelle instruction set ARM instruction set Thumb instruction set Java ByteCodes
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Directly executed bytecodes Emulated bytecodes Undefined bytecodes
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Directly executed bytecodes 140 bytecodes executed directly in HW constant loads,(iconst_0, dconst_0, …) variable loads/stores,(iload, dstore, … ) array load/stores,(iaload, dastore, … ) integer data operations(iadd, isubb, i2b, … ) branches(ifeq, icmp_ifeq, … ) quick constant pool loads(idc_quick, … ) quick static/field operations(getfield_quick, … )
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Emulated bytecodes 94 bytecodes emulated in software floating point(ddiv, dadd, dmul, … ) integer division(idiv, irem, ldiv, lrem) switch(tableswitch, lookupswitch) invoke(invokevirtual, invlkestatic, … ) return(ireturn, return, … ) new (new, newarray, … ) unresolved ldc(ldc, ldc_w, ldc2_w) unresolved field/static(getstatic, putfield, … )
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Jazelle Operation New ARM instruction: CondRm 31…283…0 BXJ Rm If Condition then J = 1, PC = Rm; enters Java state and begins Byte Code execution at (Rm)
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Jazelle Operation Addition of ‘J’ bit to CPSR: FlagsIFTModeJ 31…27244…0765 J=0 : Processor in ARM or Thumb state (depending on T bit) J=1, T=0 : Processor in Java state
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Register Re-use and Stack Optimization Use of ARM Registers in Jazelle State: R0-R3Used to cache Java expression stack R4Local variable 0 (‘this’ pointer) R5Pointer to table of SW handlers R6Java stack pointer R7Java variables pointer R8Java constant pool pointer R9-R11Reserved for JVM (not used by h/w) R12, R14Scratch usage / Java return address R13Machine stack pointer R15Java PC
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Interrupt Behavior / Real- time performance Jazelle is Compatible with ARM Programming Conventions for Interrupt Handlers: Java Program Interrupt Handler Java StateARM State CPSR->SPSR pc->r14 CPSR<-SPSR pc<-(r14-4) STM r13!, {reg. list} ; save regs used in ; interrupt handler LDM r13!, {reg, list} ; restore regs SUBS pc, r14, #4 ; return & restore state
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Support for Java Run-time Environments
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Competitor Comparison / Review of existing solutions
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Software Emulation (SUN JDK, ARM9) JIT Execution Performance CM/MHz Real-time System Performance Memory Cost Hardware Implementation Cost Legacy Code / RTOS support Software Emulation (ARM JDK, ARM9) Co-processor (eg Jedi Tech, JSTAR) Dedicated Processor ARM with architecture extensions 0.67 1.7 6.2* 2.9 3 5.5 Poor Excellent ~ 16kbyte - > 100kbyte - ~ 8kbyte - - - ~ 25k gates 20-30k gates ~ 12k gates Yes No Yes The only solution to meet all of the performance & application requirements. *Note: JIT performance excludes compilation overhead.
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ARM7TDMI
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