CMPE 325 Computer Architecture II

Name: CMPE 325 Computer Architecture II
Uploaded: 2017-08-21T07:26:37+00:00
Duration: PTM46S11
Channel: Colt Gracey
Description: CMPE 325 Computer Architecture II

CMPE 325 Computer Architecture II
Cem Ergün Eastern Mediterranean University Multiplication & Division Algorithms

Binary Multiplication
At each step we multiply the multiplicand by a single digit from the multiplier. In binary, we multiply by either 1 or 0 (much simpler than decimal). Keep a running sum instead of storing and adding all the partial products at the end. Cem Ergun Multiplication & Division Algorithms

Multiplication & Division Algorithms
Long-hand multiplication (12 × 9 = 108) = 12ten (n bit Multiplicand) × = 9ten (m bit Multiplier) = 108ten (n + m bit Product) The result is a number that is n + m - 1 bits long Cem Ergun Multiplication & Division Algorithms

Implementing Multiplication
Several different ways to implement Things to note about previous method At each step we either copied or set the value to 0 LSBs of the product don’t change once computed  Can form product by shifting and adding Solution #1 Shift multiplicand left at each step (same as adding 0’s) Shift multiplier right so we can always consider the 0’th bit Cem Ergun Multiplication & Division Algorithms

Solution #1 Multiplication without sign (12 × 9 = 108) = 12ten (n bit Multiplicand) × = 9ten (m bit Multiplier) = 108ten Multiplicand Multiplier Product Cem Ergun Multiplication & Division Algorithms

Solution #1: Operations
D o n e 1 . T s t M u l i p r a A d m c h P g 2 S f b 3 M u l t i p l i e r = 1 M u l t i p l i e r = t N o : < 3 2 r e p e t i t i o n s 3 2 n d r e p e t i t i o n ? Y e s : 3 2 r e p e t i t i o n s Cem Ergun Multiplication & Division Algorithms

Solution #1: Example Iter Step Multiplier Multiplicand Product Initial Values 1001 1 Multiplier[0]=1  Prod+Mcand 1001 Shift multiplicand left 1001 Shift multiplier right 0100 2 Multiplier[0]=0  Do nothing 0100 Shift multiplicand left 0100 Shift multiplier right 0010 3 Multiplier[0]=0  Do nothing 0010 Shift multiplicand left 0010 Shift multiplier right 0001 4 Multiplier[0]=1  Prod+Mcand 0001 Shift multiplicand left 0001 Shift multiplier right 0000 Cem Ergun Multiplication & Division Algorithms

Solution #1: Hardware Shift Left Multiplicand 64 bits Shift Right Add Multiplier 64-bit ALU 32 bits Write Product Control 64 bits Cem Ergun Multiplication & Division Algorithms

Adjustments to Algorithm 1
One big problem with the algorithm/implementation shown: need a 64 bit ALU (adder). Half of the multiplicand bits are always 0 Either high or low bits are 0, even as shifted LSB of product never changes once set Half of the 64 bit adder is therefore wasted We can fix this by: Leaving the multiplicand alone (don’t shift). Instead of shifting multiplicand left, shift the product right Add multiplicand to left half of running sum. Adder only needs to be 32 bits wide Cem Ergun Multiplication & Division Algorithms

Solution #2: Adjusted Algorithm
1 . T s t M u l i p r a A d m c h f P g 2 S b 3 ? = N : < Y Revised Addition Shift partial sum instead of multiplicand Cem Ergun Multiplication & Division Algorithms

Solution #2: Example Iter Step Multiplier Multiplicand Product Initial Values 1001 1100 1 Multiplier[0]=1  Prod+Mcand 1001 1100 Shift product right 1001 1100 Shift multiplier right 0100 1100 2 Multiplier[0]=0  Do nothing 0100 1100 Shift product right 0100 1100 Shift multiplier right 0010 1100 3 Multiplier[0]=0  Do nothing 0010 1100 Shift product right 0010 1100 Shift multiplier right 0001 1100 4 Multiplier[0]=1  Prod+Mcand 0001 1100 Shift product right 0001 1100 Shift multiplier right 0000 1100 Cem Ergun Multiplication & Division Algorithms

Solution #2: Hardware Multiplicand 32 bits Shift Right Add Multiplier 32-bit ALU 32 bits Shift Right Product Control Write 64 bits Upper 32 bits Cem Ergun Multiplication & Division Algorithms

Issues and Alternative
In the implementation of the adjusted algorithm it is possible to save space by putting the multiplier in the rightmost 32 bits of the product register. If you notice, half of the product register is useless at the beginning At the end, the multiplier register becomes useless Solution #3 The algorithm is the same, but steps 2 and 3 are done at the same time. Remove the multiplier register Place the multiplier value in the lower half of the product register Cem Ergun Multiplication & Division Algorithms

Solution #3: Operations
Cem Ergun Multiplication & Division Algorithms

Solution #3: Example Iter Step Multiplicand Product Initial Values 1100 1 Product[0]=1  Prod+Mcand 1100 Shift product right 1100 2 Product[0]=0  Do nothing 1100 Shift product right 1100 3 Product[0]=0  Do nothing 1100 Shift product right 1100 4 Product[0]=1  Prod+Mcand 1100 Shift product right 1100 Cem Ergun Multiplication & Division Algorithms

Solution #3: Hardware Multiplicand 32 bits Add 32-bit ALU Shift Right Product Control Write 64 bits Upper 32 bits Multiplier LSB Cem Ergun Multiplication & Division Algorithms

Signed Multiplication
Previous algorithms work for unsigned. We could: convert both multiplier and multiplicand to positive before starting, but remember the signs. adjust the product to have the right sign (might need to negate the product). Set the sign bit to make the number negative if the multiplicand and multiplier disagree in sign Positive × Positive = Positive Negative × Negative = Positive Positive × Negative = Negative Negative × Positive = Negative Cem Ergun Multiplication & Division Algorithms

Supporting Signed Integers
We can adjust the previous algorithm to work with signed integers make sure each shift is an arithmetic shift right shift – extend the sign bit (keep the MS bit the same instead of shifting in a 0). Since addition works for signed numbers, the multiply algorithm will now work for signed numbers. Cem Ergun Multiplication & Division Algorithms

1110 x 0011 (-2 x 3) multiplier is rightmost 4 bits Step Multiplicand Product 1110 1a 2,3 1 1st partial product in left 4 bits Shift Right Result is 2s complement Cem Ergun Multiplication & Division Algorithms

Signed Third Multiplication Algorithm

Improving the speed with Combinational Array Multiplier

Combinational Array Multiplier

Combinational Array Multiplier 3 bit Example

Booth’s Algorithm Requires that we can do an addition or a subtraction each iteration (not always an addition). Uses the following property the value of any consecutive string of 1s in a binary number can be computed with one subtraction. Cem Ergun Multiplication & Division Algorithms

A different way to compute integer values
(8-2=6) (256-8 = 248) 23 21 28 23 Cem Ergun Multiplication & Division Algorithms

A little more complex example
28 27 22 21 25 23 Cem Ergun Multiplication & Division Algorithms

An overview of Booth’s Algorithm
When doing multiplication, strings of 0s in the multiplier require only shifting (no addition). When doing multiplication, strings of 1s in the multiplier require operation and shifting. We need to add or subtract only at positions in the multiplier where there is a transition from a 0 to a 1, or from a 1 to a 0. Cem Ergun Multiplication & Division Algorithms

Booth Explanation Booth also works for negative numbers Booth Algorithm Add additional bit to the right of product Use right two bits of product to determine action Use arithmetic right shift ( ) End of string Beginning of string 1 1 1 1 Middle of string Cem Ergun Multiplication & Division Algorithms

Shifting The second step of the algorithm is the same as before: shift the product/multiplier right one bit. Arithmetic shift needed for signed arithmetic. The bit shifted off the right is saved and used by the next step 1 (which looks at 2 bits). Booth’s Algorithm Cem Ergun Multiplication & Division Algorithms

Booth Example Consider the same example, but think of it as a signed multiplication (-4×-7=28) Iter Step Multiplicand Product Initial Values 1100 1 Product=10  Prod-Mcand 1100 Shift product right 1100 2 Product=01  Prod+Mcand 1100 Shift product right 1100 3 Product=00  Do nothing 1100 Shift product right 1100 4 Product=10  Prod-Mcand 1100 Shift product right 1100 Cem Ergun Multiplication & Division Algorithms

Multiply in MIPS Product stored in two 32 bit registers called Hi and Low mult $s0, $s1 # $s0 * $s1 high/low multu $s0, $s1 # $s0 * $s1 unsigned Results are moved from Hi/Low mfhi $t0 # $t0 = Hi mflo $t0 # $t0 = Low Pseudoinstruction mul $t0, $s0, $s1 # $t0 = $s0 * $s1 Cem Ergun Multiplication & Division Algorithms

Divide Long-hand division (108 ÷ 12 = 9) (n bit Quotient) | (Divisor) | (Dividend) (Remainder) N + 1 Steps Cem Ergun Multiplication & Division Algorithms

Divide Solution #1 Solution #1 Start with quotient = 0, remainder = dividend, and divisor’s top bits set On each iteration set remainder to be remainder – divisor If large enough (remainder  0), then shift quotient left and set rightmost to 1 If not large enough (remainder < 0), then set remainder to remainder + divisor (restore) Shift divisor right Continue for n+1 (33) iterations rem = rem - div if rem < 0 then // divisor too big rem = rem + div quo <<= 1 LSB(quo) = 0 else // can divide LSB(quo) = 1 fi div >>= 1 repeat unless done Cem Ergun Multiplication & Division Algorithms

Divide Solution #1 Cem Ergun Multiplication & Division Algorithms

Solution #1: Hardware Shift Right Divisor 64 bits Shift Left Quotient 64-bit ALU 32 bits Write Remainder Control 64 bits MSB Cem Ergun Multiplication & Division Algorithms

/ 0010 Step Quotient Divisor Remainder 0000 1 2b 3 2a 0001 0011 initial values after subtraction after restore shift right final remainder final quotient Cem Ergun Multiplication & Division Algorithms

Division Example: /0101 Initial Values (Divisor in LHS) Quotient Divisor Remainder xxxx 1a. Rem. <-- Rem-Divisor - 1b. Rem.<0, Add Div., LSh Q, Q0=0; RSh Div. xxxx 1 2a. Rem. <-- Rem-Divisor xxx 2b. Rem>=0, LSh Q, Q0=1; RSh Div. - 3a. Rem. <-- Rem-Divisor xxx 2 3b. Rem>=0, LSh Q, Q0=1; RSh Div. xx - 4a. Rem. <-- Rem-Divisor xx 3 4b. Rem>=0, LSh Q, Q0=1; RSh Div. 5a. Rem. <-- Rem-Divisor x - 5b. Rem<0, Add Div., LSh Q, Q0=0; RSh Div. x 4 Control 64-bit Remainder 64 bit Write Divisor ShRight Quotient 32 bit ShLeft - 5 /0101 = 1110 rem /5 = 14 rem 3 N+1 Steps, but first step cannot produce a 1. Cem Ergun Multiplication & Division Algorithms

Just as before Half of the divisor bits are always 0 Either high or low bits are 0, even as shifted Half of the 64 bit adder is therefore wasted Solution #2 Instead of shifting divisor right, shift the remainder left Adder only needs to be 32 bits wide Can also remove iteration by switching order to shift and then subtract Remainder is in left half of register Cem Ergun Multiplication & Division Algorithms

Solution #2: Hardware Divisor 32 bits Shift Left Quotient 32-bit ALU 32 bits Shift Left Remainder Control Write 64 bits MSB Cem Ergun Multiplication & Division Algorithms

Improved Divider: /0101 Initial Values Quotient Divisor Remainder xxxx 0. LSh Rem 1a. Rem. <-- Rem-Divisor xxxx x - 1b. Rem>=0, LSh Q, Q0=1; LSh Rem. xxxx x 1 2a. Rem. <-- Rem-Divisor xxx xx 2b. Rem>=0, LSh Q, Q0=1; LSh Rem. - xxx xx 3a. Rem. <-- Rem-Divisor 2 3b. Rem>=0, LSh Q, Q0=1; LSh Rem. xx xxx - 4a. Rem. <-- Rem-Divisor xx xxx 3 4b. Rem<0, Add Div., LSh Q, Q0=0 x xxxx - Control 32-bit LH Rem. 64 bit Write Divisor 32 bit Quotient ShLeft RH Rem. x xxxx 4 xxxx /0101 = 1110 rem /5 = 14 rem 3 Cem Ergun Multiplication & Division Algorithms

Just as before, half of the remainder register is useless at the beginning At the end, the quotient register becomes useless Solution #3 Remove the quotient register Place the quotient in the lower half of the remainder register Need to unshift in the last step to account for off-by-one Cem Ergun Multiplication & Division Algorithms

Further Modifications Solution#3
Same space savings as with multiplication: use right ½ of remainder register to hold the quotient. W r i t e 3 2 b s 6 4 S h f l g R m a n d - A L U D v o C quotient Cem Ergun Multiplication & Division Algorithms

Divide Solution #3 D o n e . S h i f t l a R m d r g 1 b T s 3 , w 2 p ? < N : 1 . S h i f t t h e R e m a i n d e r r e g i s t e r l e f t 1 b i t rem <<= 1 rem -= (div >> 32) if rem < 0 then rem += (div >> 32) LSB(rem) = 0 else LSB(rem) = 1 fi repeat unless done Correct remainder g i s t e r . A l o h f R m a n d , w b 2 S u c D v p f t h a l f o f t h e R e m a i n d e r r e g i s t e r R e m a i n d e r > – < 3 2 r e p t i o n s Y : b . R h g a l v u y d D f m c Cem Ergun Multiplication & Division Algorithms

Solution #3: Example Cem Ergun Multiplication & Division Algorithms

Improved Improved Divider: 1001001/0101
Initial Values Divisor Remainder-Quotient 0. LSh Rem-Quo. 1a. Rem <-- Rem-Divisor - 1b. Rem>=0, LSh Rem-Quo, Q0=1 1 2a. Rem. <-- Rem-Divisor 2b. Rem>=0, LSh Rem-Quo, Q0=1 - 3a. Rem. <-- Rem-Divisor 2 3b. Rem>=0, LSh Rem-Quo, Q0=1 - 4a. Rem. <-- Rem-Divisor 3 4b. Rem<0, Add Div., LSh Rem-Quo, Q0=0 - Control 32-bit LH Rem. 64 bit Write Divisor 32 bit ShLeft Rem-Quot. 4 Final: RSh Rem 1 /0101 = 1110 rem /5 = 14 rem 3 Cem Ergun Multiplication & Division Algorithms

Signed Division Same process as naïve integer multiply Make divisor and dividend positive Negate quotient if signs of divisor and dividend disagree Set sign of remainder Dividend = Quotient × Divisor + Remainder Sign should match dividend Cem Ergun Multiplication & Division Algorithms

Divide in MIPS Quotient/Remainder stored in two 32 bit registers called Hi and Low div $s0, $s1 # $s0 / $s1 high/low divu $s0, $s1 # $s0 / $s1 unsigned Results are moved from Hi/Low mfhi $t0 # $t0 = Hi mflo $t0 # $t0 = Low Pseudoinstructions div $t0, $s0, $s1 # $t0 = $s0 / $s1 rem $t0, $s0, $s1 # $t0 = $s0 % $s1 div $s0,$s1 Lo = $s0/$s1 (integer) Hi = $s0 % $s1 Cem Ergun Multiplication & Division Algorithms

CMPE 325 Computer Architecture II

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