1. 20 July 2006 H. Chanal, R. Cornat, E. Delage, O. Deschamps, J. Laubser, M. Magne, P. Perret LPC Clermont Level 0 Decision Unit PRR

2. Agenda  Introduction  L0DU board design: Julien  GPL board design: Hervé/Magali  L0DU board tests: Olivier  Production and tests

3. L0DU Functionalities  Aim: Reduce the data flow down to 1 MHz for the next trigger level  The L0DU receives @ 40 MHz information from L0 sub-triggers: - L0 Calorimeter selection board - L0 Muon trigger processor - L0 Pile-Up system  I/O are fully synchronous  A total of 24*32 bits at 40 MHz are expected as input of the L0DU  Actually 17*32 are used  A physics algorithm is applied to select events and to deliver the L0DU decision @ 40 MHz to the Readout Supervisor

4. L0DU Outlook  Work on L0DU has started in 1998!  A first prototype (and its test bench) was done in 2002 and successfully tested  96 inputs; parallel RJ45 …

5. L0DU Outlook  It was decided to switch to optical inputs (TDR time)  This was not trivial !  A new prototype (full scale) has been designed in 2004  Long test phase needed:  We had to learn optical links and their debug  It was necessary to design a dedicated (optical) test bench in July 2005  Huge over costs covered thanks to special funding from

6. L0DU Overview INPUT data: (24 words 32 bits) Optical links: 16-bit data @ 80 MHz →1.6Gb/s serial data 2x12 fiber ribbons  up to 24 inputs HFBR & TLK2501 TTC CALO MUON Pile-Up DATA processing: 3 FPGA:  1: interface & supervisor  2: treatment 782782 +7 spares Patch Panel Single fibers Optical ribbons

7. L0DU Overview (con’t) OUTPUT data:  RS: 16 bits @ 40 MHz Parallel, 3M connector L0DU as a TELL1 mezzanine  HLT: TELL1 Board QTS connectors! L0accept Control data:  From TELL1: CC/PC + JTAG  From external PC:USB + Power distribution

8. L0accept From Trigger processors To Readout Supervisor 100% on the mezzanine From L0DU PGAs To HLT Data sent through TELL1 From TELL1/CC-PC Or From external PC/USB (independent debugging) L0DU Data Flow MAIN DATA FLOW HLT DATA FLOW CONTROL FLOW

9. At 40 MHz it receives in parallel: CALO: e, ,  0 L,  0 G,h,E T,N spd Muons: 8 cand.  Vertex: pile-up  768 bits @ 40MHz 7 8 2 7 : 24 words of 32 bits OUTPUT: RS, HLT (TELL1) L0DU Architecture 224@40MHz 1024@1MHz

10. PDP:  Time alignment  Data preparation for algorithms 7 8 2 7 : 24 words of 32 bits OUTPUT: RS, HLT (TELL1) L0DU Architecture 224@40MHz 1024@1MHz TDU:  Trigger conditions elaboration  Decision computation

11. Flexible Architecture Try to implement a flexible architecture for upgrade, change of algorithms The idea: Set of variables Set of logical operators µ 1 µ 2.. e γ π 0 h E T Pile-Up > = x + < & … + Threshold can be duplicated several times Possible to combine them “as we’d like” to elaborate a trigger condition (without reprogramming FPGA)

12. L0DU Tests  It is mandatory to have a fast an easy L0DU test system and a complete one:  An internal test bench to allow a fast debugging  A dedicated test bench for a full debug based on a Generator Pattern injection for L0DU (GPL) board specially designed for this purpose and permanently available L0DU implementation Readout Supervisor rack Patch Panel ODINODIN GPLGPL L0DUL0DU Ribbon cable Slot reserved: - 2 for L0DU - 2 for GPL - 1 spare reserved