1. B159- MAPLD - 2004Burke1 Operation of FPGAs at Extremely Low Temperatures Gary Burke, Scott Cozy, Veronica Lacayo, Alireza Bakhshi, Ryan Stern, Mohammad Mojarradi, Travis Johnson, Elizabeth Kolawa, Gary Bolotin, Tim Gregoire, and Rajeshuni Ramesham Jet Propulsion Laboratory, California Institute of Technology

2. B159- MAPLD - 2004Burke2 Purpose of Cold temperature Testing The surface temperature of Mars can vary from -120  C to +20  C. In order to use qualified parts on a Mars Rover such as MER, it is necessary to enclose them in a protective box, known as a ‘warm-box’, where the temperature is controlled by resistive heating elements. This approach results in complex wiring, adding to mass and creating test problems

3. B159- MAPLD - 2004Burke3 Why Cold-Temperature FPGAs The wiring could be simplified, if a bus system is used to send commands to control the peripherals. However, this then requires bus controllers to be outside of the warm-box, and subject to ambient temperatures. These controllers can be conveniently implemented with FPGAs

4. B159- MAPLD - 2004Burke4 Types of test Can the FPGA operate normally at cold? Can the FPGA be powered up at cold? Does the FPGA performance degrade over time? Will the FPGA package withstand the cold temperature and temperature cycling? –These are still being investigated

5. B159- MAPLD - 2004Burke5 Devices tested - Actel ACTEL FPGA Density (System Gate) RAMRadiation TID: krad(Si) Package TMR Temp (°C) RT54SX72S * 108 KNo100208-Pin Ceramic Quad FP Yes-55 to +125 A54SX32A48 KNo 144 Thin Quad FPNo-40 to +85 * No results yet

6. B159- MAPLD - 2004Burke6 Devices tested - Xilinx FPGA XilinxDensityRAMRadiation TID: krad(Si) PackageEmbed ded Power PC Temp (°C) XQVR600 (tests in progress) 661 K gates Yes100228-Pin Ceramic Quad FP No-55 to +125 XCVR600661 K gates YesNo240-Pin High Heat Dissipation Quad FP No-40 to +100 XC2VP20- FF1152 9280 slices YesNo1152 -pin fine- pitched BGA 20 to +85

7. B159- MAPLD - 2004Burke7 Test setup

8. B159- MAPLD - 2004Burke8 FPGA Board Test Set Up -ACTEL

9. B159- MAPLD - 2004Burke9 FPGA Board Test Set Up - Xilinx

10. B159- MAPLD - 2004Burke10 Wire Wrap Board Test Set Up - Xilinx

11. B159- MAPLD - 2004Burke11 Wire Wrap Board Test Set Up - ACTEL

12. B159- MAPLD - 2004Burke12 Test Code – Actel and Virtex Test Code is Dual Counters A ‘Fail’ bit is set if ms bits of counter do not match MSB bits and ‘fail’ are displayed on LEDs to give instant fail information A set of registers is used to perform read/write tests

13. B159- MAPLD - 2004Burke13 Test Code – Actel and Virtex Additional test outputs are programmed to allow testing of combinational delays Clock skew can be measured via test outputs (Note: Xilinx Pro – has different test code)

14. B159- MAPLD - 2004Burke14 Actel Results Commercial Actel FPGA (A54SX32A) results: Digital logic –functioned down to –165ºC Power cycling –functioned to –165ºC

15. B159- MAPLD - 2004Burke15 Virtex Results Commercial Xilinx FPGA (XCVR600) results: Digital logic –functioned down to –165ºC Power cycling –initialization current increased from 10 mA at 0ºC to 800 mA (current limited) at –40ºC, and FPGA failed to initialize. Further tests were performed on this part.

16. B159- MAPLD - 2004Burke16 Virtex Surge Current Test The Xilinx Virtex part exhibits startup surge current which increases at cold temperature The power supply limits (800 mA) prevents Xilinx part from configuring at cold temp. A further test was performed on the Xilinx Virtex part to measure surge current Setup was the same but larger power supplies and larger power cabling were used

17. B159- MAPLD - 2004Burke17 Surge current at 20ºC

18. B159- MAPLD - 2004Burke18 Surge current at -40˚C

19. B159- MAPLD - 2004Burke19 Surge current at -92˚C

20. B159- MAPLD - 2004Burke20 Surge current at -140˚C

21. B159- MAPLD - 2004Burke21 Surge current vs. temperature

22. B159- MAPLD - 2004Burke22 Surge current summary The startup current is temperature dependant The current peaks at –92ºC (5.22Amps) At lower temperatures the startup current decreases from the peak The width of the current pulse has the same temperature dependence As long as sufficient current is supplied, the Virtex part is able to be powered on and configured down to –140 ºC

23. B159- MAPLD - 2004Burke23 Temperature Test for the Virtex-II PP Board The purpose for testing this board at low temperatures was to initially find out if the board and mainly the Virtex-II Pro FPGA part number XC2VP20-FF1152 would survive and continue operating at different temperature ranges. An additional test was to power off the board once it reached -120ºC and to see what happens when powered back. Based on Virtex testing, the FPGA was suspected to drain a lot of current of up to 10A.

24. B159- MAPLD - 2004Burke24 Temperature Test for the Virtex-II PP Board The Virtex-II PP Board was tested at different temperatures. The temperature range went from 25ºC to -120ºC. For this particular test, the board was powered using 3 power supplies. They were set up at the following voltages: –3.3Vdc –2.5Vdc and –1.5Vdc. Surge current was measured on the 1.5V supply.

25. B159- MAPLD - 2004Burke25 Temperature Test for the Virtex-II PP Board

26. B159- MAPLD - 2004Burke26 Temperature Test for the Virtex-II PP Board The 3.3Vdc supplied power to the Electronics in the board. The 2.5Vdc supplied power to the I/O’s, banks, and Rocket I/O Transceivers. The 1.5Vdc supplied power to the FPGA core. The test FPGA circuit runs self checking firmware on 2 embedded processors, monitored via RS232 port

27. B159- MAPLD - 2004Burke27 Temperature Test for the Virtex-II PP Board The following values were measured before the test at room temperature (22.7ºC) in the lab. –V = 3.3V at 110mA. –V = 2.5V between 35mA and 41mA. –V = 1.5V at 221mA.

28. B159- MAPLD - 2004Burke28 Temperature Test for the Virtex-II PP Board The following are Voltage readings taken at different temperatures: –T0 = -5ºC, T1 = -2.4ºC and T2 = -1.8ºC: V = 3.3V at 110mA. V = 2.5V between 35mA and 41mA. V = 1.5V at 210mA. –T0 = -55.8ºC, T1 = -50ºC and T2 = -50.4ºC: V = 3.3V at 99mA. V = 2.5V between 35mA and 41mA. V = 1.5V at 210mA. –T0 = -121.7ºC, T1 = -117.7ºC and T2 = -115.9ºC: V = 3.3V at 96mA. V = 2.5V between 35mA and 41mA. V = 1.5V at 208mA.

29. B159- MAPLD - 2004Burke29 Temperature Test for the Virtex-II PP Board The board was never shut down as the temperature was decreased. The board never stopped working. Once it reached -120ºC, the temperature was brought back up. At intervals, we power cycle the board and measure the in rush current. It was found as temperature ramped up that the board always powered back on. At times, it was necessary to press the configuration switch, to reset the board

30. B159- MAPLD - 2004Burke30 Temperature Test for the Virtex-II PP Board T0 = -121.7ºC, T1 = -117.7ºC and T2 = -115.9ºC. At power on, the in rush current was of approximately 220mA for about 0.3ms then it drops to 170mV for about 22ms.

31. B159- MAPLD - 2004Burke31 Temperature Test for the Virtex-II PP Board T0 = -58.8ºC, T1 = -60.5ºC and T2 = -59.3ºC. There was no change in inrush current.

32. B159- MAPLD - 2004Burke32 Temperature Test for the Virtex-II PP Board T0= 21.9ºC, T1 = 16.9ºC and T2 = 16.8ºC. The in rush current never changed through-out the temperatures tested.

33. B159- MAPLD - 2004Burke33 Temperature Test for the Virtex-II PP Board The Virtex II Pro functioned correctly at temperatures down to –120ºC (limit of testing) The Virtex II Pro FPGA did not show a large rush current. The current peaked at 220mA. The excessive startup surge current seen on the Virtex chip at cold temperatures is not seen on the Virtex II Pro.

34. B159- MAPLD - 2004Burke34 Summary All 3 of the FPGAs tested both Actel and Xilinx were functional down to –120ºC or lower. A large startup surge current was seen on the Xilinx Virtex part at cold temperatures. –If this current is not supplied, the part will not configure The Xilinx Virtex II Pro does not have the surge current problem.