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1 Seoul National University Wrap-Up. 2 Overview Seoul National University Wrap-Up of PIPE Design  Exception conditions  Performance analysis Modern.

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Presentation on theme: "1 Seoul National University Wrap-Up. 2 Overview Seoul National University Wrap-Up of PIPE Design  Exception conditions  Performance analysis Modern."— Presentation transcript:

1 1 Seoul National University Wrap-Up

2 2 Overview Seoul National University Wrap-Up of PIPE Design  Exception conditions  Performance analysis Modern High-Performance Processors  Out-of-order execution

3 3 Exceptions Seoul National University  Conditions under which processor cannot continue normal operation Causes  Halt instruction(Current)..  Bad address for instruction or data(Previous)  Invalid instruction(Previous) Typical Desired Action  Complete instructions  Either current or previous (depends on exception type)  Discard others  Call exception handler  Like an unexpected procedure call Our Implementation  Halt when instruction causes exception

4 4 Exception Examples Seoul National University irmovl $100,%eax rmmovl %eax,0x10000(%eax) # invalid address jmp $-1 # Invalid jump target.byte 0xFF # Invalid instruction code halt # Halt instruction

5 5 Exceptions in Pipeline Processor #1 Seoul National University Desired Behavior  rmmovl should cause exception  Following instructions should have no effect on processor state irmovl $100,%eax rmmovl %eax,0x10000(%eax) # Invalid address nop.byte 0xFF # Invalid instruction code 0x000: irmovl $100,%eax 1234 FDEM FDE 0x006: rmmovl %eax,0x1000(%eax) 0x00c: nop 0x00d:.byte 0xFF FD F W 5 M E D Exception detected

6 6 Exceptions in Pipeline Processor #2 Seoul National University Desired Behavior  No exception should occur 0x000: xorl %eax,%eax # Set condition codes 0x002: jne t # Not taken 0x007: irmovl $1,%eax 0x00d: irmovl $2,%edx 0x013: halt 0x014: t:.byte 0xFF # Target 0x000: xorl %eax,%eax 123 FDE FD 0x002: jne t 0x014: t:.byte 0xFF 0x???: (I’m lost!) F Exception detected 0x007: irmovl $1,%eax 4 M E F D W 5 M D F E E D M 6 M E W 7 W M 8 W 9

7 7 Maintaining Exception Ordering Seoul National University  Add status field to pipeline registers  Fetch stage sets to either “AOK,” “ADR” (when bad fetch address), “HLT” (halt instruction) or “INS” (illegal instruction)  Decode & execute pass values through  Memory either passes through or sets to “ADR”  Exception triggered only when instruction hits write back F predPC W icodevalEvalMdstEdstMstat M CndicodevalEvalAdstEdstMstat E icodeifunvalCvalAvalBdstEdstMsrcAsrcBstat D rBvalCvalPicodeifunrAstat

8 8 Side Effects in Pipeline Processor Seoul National University Desired Behavior  rmmovl should cause exception  No following instruction should have any effect irmovl $100,%eax rmmovl %eax,0x10000(%eax) # invalid address addl %eax,%eax # Sets condition codes 0x000: irmovl $100,%eax 1234 FDEM FDE 0x006: rmmovl %eax,0x1000(%eax) 0x00c: addl %eax,%eax FD W 5 M E Exception detected Condition code set

9 9 Avoiding Side Effects Seoul National University Presence of Exception Should Disable State Update  Invalid instructions are converted to pipeline bubbles  Except have stat indicating exception status  Data memory will not write to invalid address  Prevent invalid update of condition codes  Detect exception in memory stage  Disable condition code setting in execute  Must happen in same clock cycle

10 10 Rest of Real-Life Exception Handling Seoul National University Call Exception Handler  Push PC onto stack  Either PC of faulting instruction or of next instruction  Usually pass through pipeline along with exception status  Jump to handler address  Usually fixed address  Defined as part of ISA

11 11 Performance of Pipelined Processor Seoul National University Clock rate  Measured in Gigahertz  Function of stage partitioning and circuit design  Keep amount of work per stage small Rate at which instructions executed  CPI: cycles per instruction  On average, how many clock cycles does each instruction require?  Function of pipeline design and benchmark programs  E.g., how frequently are branches mispredicted?

12 12 CPI for PIPE Seoul National University CPI  1.0  Fetch instruction each clock cycle  Effectively process new instruction almost every cycle  Although each individual instruction has latency of 5 cycles CPI > 1.0  Sometimes must stall or cancel branches Computing CPI  C clock cycles  I instructions executed to completion  B bubbles injected (C = I + B) CPI = C/I = (I+B)/I = 1.0 + B/I  Factor B/I represents average penalty due to bubbles

13 13 CPI for PIPE (Cont.) Seoul National University B/I = LP + MP + RP  LP: Penalty due to load/use hazard stalling  Fraction of instructions that are loads0.25  Fraction of load instructions requiring stall0.20  Number of bubbles injected each time1  LP = 0.25 * 0.20 * 1 = 0.05  MP: Penalty due to mispredicted branches  Fraction of instructions that are cond. jumps 0.20  Fraction of cond. jumps mispredicted0.40  Number of bubbles injected each time 2  MP = 0.20 * 0.40 * 2 = 0.16  RP: Penalty due to ret instructions  Fraction of instructions that are returns0.02  Number of bubbles injected each time 3  RP = 0.02 * 3 = 0.06  Net effect of penalties 0.05 + 0.16 + 0.06 = 0.27  CPI = 1.27 (Not bad!) Typical Values

14 14 Modern CPU Design Seoul National University Execution Functional Units Instruction Control Integer/ Branch FP Add FP Mult/Div LoadStore Instruction Cache Data Cache Fetch Control Instruction Decode Address Instructions Operations Prediction OK? Data Addr.. General Integer Operation Results Retirement Unit Register File Register Updates

15 15 Instruction Control Seoul National University Grabs Instruction Bytes From Memory  Based on Current PC + Predicted Targets for Predicted Branches  Hardware dynamically guesses whether branches taken/not taken and (possibly) branch target Translates Instructions Into Operations  Primitive steps required to perform instruction  Typical instruction requires 1–3 operations Converts Register References Into Tags  Abstract identifier linking destination of one operation with sources of later operations Instruction Control Instruction Cache Fetch Control Instruction Decode Address Instructions Operations Retirement Unit Register File Instruction Control Instruction Cache Fetch Control Instruction Decode Address Instructions Operations Retirement Unit Register File

16 16 Execution Unit Seoul National University  Multiple functional units  Each can operate in independently  Operations performed as soon as operands available  Not necessarily in program order  Within limits of functional units  Control logic  Ensures behavior equivalent to sequential program execution Execution Functional Units Integer/ Branch FP Add FP Mult/Div LoadStore Data Cache Prediction OK? Data Addr.. General Integer Operation Results Register Updates Operations

17 17 Dynamic Branch Prediction Seoul National University Branch History  Encode information about prior history of branch instructions  Predict whether or not branch will be taken State Machine  Each time branch taken, transition to right  When not taken, transition to left  Predict branch taken when in state Yes! or Yes? TTT Yes!Yes?No?No! NT T

18 18 Processor Summary Seoul National University Design Technique  Create uniform framework for all instructions  Want to share hardware among instructions  Connect standard logic blocks with bits of control logic Operation  State held in memories and clocked registers  Computation done by combinational logic  Clocking of registers/memories sufficient to control overall behavior Enhancing Performance  Pipelining increases throughput and improves resource utilization  Must make sure to maintain ISA behavior

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